2006-04-27 23:07:38 +02:00
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/*
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* SH4 emulation
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2007-09-16 23:08:06 +02:00
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*
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2006-04-27 23:07:38 +02:00
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* Copyright (c) 2005 Samuel Tardieu
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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2019-02-13 14:52:50 +01:00
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* version 2.1 of the License, or (at your option) any later version.
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2006-04-27 23:07:38 +02:00
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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2009-07-16 22:47:01 +02:00
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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2006-04-27 23:07:38 +02:00
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*/
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2016-01-26 19:17:20 +01:00
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#include "qemu/osdep.h"
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2006-04-27 23:07:38 +02:00
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#include "cpu.h"
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2016-03-15 13:18:37 +01:00
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#include "exec/exec-all.h"
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2016-01-07 14:55:28 +01:00
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#include "exec/log.h"
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2017-05-17 00:48:18 +02:00
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#include "sysemu/sysemu.h"
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2011-11-17 14:23:01 +01:00
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#if !defined(CONFIG_USER_ONLY)
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2013-02-05 17:06:20 +01:00
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#include "hw/sh4/sh_intc.h"
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2011-11-17 14:23:01 +01:00
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#endif
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2006-04-27 23:07:38 +02:00
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#define MMU_OK 0
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#define MMU_ITLB_MISS (-1)
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#define MMU_ITLB_MULTIPLE (-2)
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#define MMU_ITLB_VIOLATION (-3)
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#define MMU_DTLB_MISS_READ (-4)
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#define MMU_DTLB_MISS_WRITE (-5)
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#define MMU_DTLB_INITIAL_WRITE (-6)
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#define MMU_DTLB_VIOLATION_READ (-7)
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#define MMU_DTLB_VIOLATION_WRITE (-8)
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#define MMU_DTLB_MULTIPLE (-9)
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#define MMU_DTLB_MISS (-10)
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2008-11-21 23:33:15 +01:00
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#define MMU_IADDR_ERROR (-11)
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#define MMU_DADDR_ERROR_READ (-12)
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#define MMU_DADDR_ERROR_WRITE (-13)
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2006-04-27 23:07:38 +02:00
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2019-04-02 17:18:39 +02:00
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#if defined(CONFIG_USER_ONLY)
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void superh_cpu_do_interrupt(CPUState *cs)
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{
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cs->exception_index = -1;
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}
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int cpu_sh4_is_cached(CPUSH4State *env, target_ulong addr)
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{
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/* For user mode, only U0 area is cacheable. */
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return !(addr & 0x80000000);
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}
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#else /* !CONFIG_USER_ONLY */
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2013-02-02 10:57:51 +01:00
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void superh_cpu_do_interrupt(CPUState *cs)
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2006-04-27 23:07:38 +02:00
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{
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2013-02-02 10:57:51 +01:00
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SuperHCPU *cpu = SUPERH_CPU(cs);
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CPUSH4State *env = &cpu->env;
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2013-01-17 18:51:17 +01:00
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int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD;
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2013-08-26 08:31:06 +02:00
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int do_exp, irq_vector = cs->exception_index;
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2007-12-02 07:18:24 +01:00
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/* prioritize exceptions over interrupts */
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2013-08-26 08:31:06 +02:00
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do_exp = cs->exception_index != -1;
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do_irq = do_irq && (cs->exception_index == -1);
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2007-12-02 07:18:24 +01:00
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2015-05-25 01:28:56 +02:00
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if (env->sr & (1u << SR_BL)) {
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2013-08-26 08:31:06 +02:00
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if (do_exp && cs->exception_index != 0x1e0) {
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2017-05-17 00:48:18 +02:00
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/* In theory a masked exception generates a reset exception,
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which in turn jumps to the reset vector. However this only
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works when using a bootloader. When using a kernel and an
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initrd, they need to be reloaded and the program counter
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should be loaded with the kernel entry point.
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qemu_system_reset_request takes care of that. */
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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return;
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2007-12-02 07:18:24 +01:00
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}
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2011-02-24 12:31:41 +01:00
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if (do_irq && !env->in_sleep) {
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2007-12-02 07:18:24 +01:00
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return; /* masked */
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}
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}
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2011-02-24 12:31:41 +01:00
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env->in_sleep = 0;
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2007-12-02 07:18:24 +01:00
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if (do_irq) {
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irq_vector = sh_intc_get_pending_vector(env->intc_handle,
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(env->sr >> 4) & 0xf);
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if (irq_vector == -1) {
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return; /* masked */
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}
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}
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2009-01-15 23:36:53 +01:00
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if (qemu_loglevel_mask(CPU_LOG_INT)) {
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2006-04-27 23:07:38 +02:00
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const char *expname;
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2013-08-26 08:31:06 +02:00
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switch (cs->exception_index) {
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2006-04-27 23:07:38 +02:00
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case 0x0e0:
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expname = "addr_error";
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break;
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case 0x040:
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expname = "tlb_miss";
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break;
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case 0x0a0:
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expname = "tlb_violation";
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break;
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case 0x180:
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expname = "illegal_instruction";
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break;
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case 0x1a0:
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expname = "slot_illegal_instruction";
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break;
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case 0x800:
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expname = "fpu_disable";
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break;
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case 0x820:
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expname = "slot_fpu";
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break;
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case 0x100:
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expname = "data_write";
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break;
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case 0x060:
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expname = "dtlb_miss_write";
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break;
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case 0x0c0:
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expname = "dtlb_violation_write";
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break;
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case 0x120:
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expname = "fpu_exception";
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break;
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case 0x080:
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expname = "initial_page_write";
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break;
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case 0x160:
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expname = "trapa";
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break;
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default:
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2007-12-02 07:18:24 +01:00
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expname = do_irq ? "interrupt" : "???";
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break;
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2006-04-27 23:07:38 +02:00
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}
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2009-01-15 23:34:14 +01:00
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qemu_log("exception 0x%03x [%s] raised\n",
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irq_vector, expname);
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2013-06-16 07:28:50 +02:00
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log_cpu_state(cs, 0);
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2006-04-27 23:07:38 +02:00
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}
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2015-05-25 01:28:56 +02:00
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env->ssr = cpu_read_sr(env);
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2007-12-02 07:18:24 +01:00
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env->spc = env->pc;
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2006-04-27 23:07:38 +02:00
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env->sgr = env->gregs[15];
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2015-05-25 01:28:56 +02:00
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env->sr |= (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB);
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2017-09-07 20:50:53 +02:00
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env->lock_addr = -1;
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2006-04-27 23:07:38 +02:00
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2017-05-17 00:48:18 +02:00
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if (env->flags & DELAY_SLOT_MASK) {
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2008-08-22 10:57:35 +02:00
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/* Branch instruction should be executed again before delay slot. */
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env->spc -= 2;
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/* Clear flags for exception/interrupt routine. */
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2017-05-17 00:48:18 +02:00
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env->flags &= ~DELAY_SLOT_MASK;
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2008-08-22 10:57:35 +02:00
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}
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2007-12-02 07:18:24 +01:00
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if (do_exp) {
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2013-08-26 08:31:06 +02:00
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env->expevt = cs->exception_index;
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switch (cs->exception_index) {
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2007-12-02 07:18:24 +01:00
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case 0x000:
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case 0x020:
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case 0x140:
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2015-05-25 01:28:56 +02:00
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env->sr &= ~(1u << SR_FD);
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2007-12-02 07:18:24 +01:00
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env->sr |= 0xf << 4; /* IMASK */
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env->pc = 0xa0000000;
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break;
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case 0x040:
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case 0x060:
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env->pc = env->vbr + 0x400;
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break;
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case 0x160:
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env->spc += 2; /* special case for TRAPA */
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/* fall through */
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default:
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env->pc = env->vbr + 0x100;
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break;
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}
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return;
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}
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if (do_irq) {
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env->intevt = irq_vector;
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env->pc = env->vbr + 0x600;
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return;
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2006-04-27 23:07:38 +02:00
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}
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}
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2012-03-14 01:38:22 +01:00
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static void update_itlb_use(CPUSH4State * env, int itlbnb)
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2006-04-27 23:07:38 +02:00
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{
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uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
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switch (itlbnb) {
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case 0:
|
2008-05-09 20:45:55 +02:00
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and_mask = 0x1f;
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2006-04-27 23:07:38 +02:00
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break;
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case 1:
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and_mask = 0xe7;
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or_mask = 0x80;
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break;
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case 2:
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and_mask = 0xfb;
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or_mask = 0x50;
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break;
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case 3:
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or_mask = 0x2c;
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break;
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}
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2008-05-09 20:45:55 +02:00
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env->mmucr &= (and_mask << 24) | 0x00ffffff;
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2006-04-27 23:07:38 +02:00
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env->mmucr |= (or_mask << 24);
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}
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2012-03-14 01:38:22 +01:00
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static int itlb_replacement(CPUSH4State * env)
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2006-04-27 23:07:38 +02:00
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{
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2013-09-03 17:38:47 +02:00
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SuperHCPU *cpu = sh_env_get_cpu(env);
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if ((env->mmucr & 0xe0000000) == 0xe0000000) {
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2006-04-27 23:07:38 +02:00
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return 0;
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2013-09-03 17:38:47 +02:00
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}
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if ((env->mmucr & 0x98000000) == 0x18000000) {
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2006-04-27 23:07:38 +02:00
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return 1;
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2013-09-03 17:38:47 +02:00
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}
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if ((env->mmucr & 0x54000000) == 0x04000000) {
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2006-04-27 23:07:38 +02:00
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return 2;
|
2013-09-03 17:38:47 +02:00
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}
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if ((env->mmucr & 0x2c000000) == 0x00000000) {
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2006-04-27 23:07:38 +02:00
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return 3;
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2013-09-03 17:38:47 +02:00
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}
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cpu_abort(CPU(cpu), "Unhandled itlb_replacement");
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2006-04-27 23:07:38 +02:00
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}
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/* Find the corresponding entry in the right TLB
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Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
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*/
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2012-03-14 01:38:22 +01:00
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static int find_tlb_entry(CPUSH4State * env, target_ulong address,
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2006-04-27 23:07:38 +02:00
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tlb_t * entries, uint8_t nbtlb, int use_asid)
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{
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int match = MMU_DTLB_MISS;
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uint32_t start, end;
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uint8_t asid;
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int i;
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asid = env->pteh & 0xff;
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for (i = 0; i < nbtlb; i++) {
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if (!entries[i].v)
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continue; /* Invalid entry */
|
2008-12-10 18:31:51 +01:00
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if (!entries[i].sh && use_asid && entries[i].asid != asid)
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2006-04-27 23:07:38 +02:00
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continue; /* Bad ASID */
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start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
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end = start + entries[i].size - 1;
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if (address >= start && address <= end) { /* Match */
|
2008-05-09 20:45:55 +02:00
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if (match != MMU_DTLB_MISS)
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2006-04-27 23:07:38 +02:00
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return MMU_DTLB_MULTIPLE; /* Multiple match */
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match = i;
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}
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}
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return match;
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}
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2012-03-14 01:38:22 +01:00
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static void increment_urc(CPUSH4State * env)
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2008-08-22 10:57:43 +02:00
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{
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uint8_t urb, urc;
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/* Increment URC */
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urb = ((env->mmucr) >> 18) & 0x3f;
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urc = ((env->mmucr) >> 10) & 0x3f;
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urc++;
|
2009-03-03 10:14:01 +01:00
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if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1))
|
2008-08-22 10:57:43 +02:00
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urc = 0;
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env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
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}
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|
2011-01-09 23:53:45 +01:00
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/* Copy and utlb entry into itlb
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Return entry
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*/
|
2012-03-14 01:38:22 +01:00
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static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
|
2011-01-09 23:53:45 +01:00
|
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{
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int itlb;
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tlb_t * ientry;
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itlb = itlb_replacement(env);
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ientry = &env->itlb[itlb];
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if (ientry->v) {
|
2013-09-04 01:29:02 +02:00
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tlb_flush_page(CPU(sh_env_get_cpu(env)), ientry->vpn << 10);
|
2011-01-09 23:53:45 +01:00
|
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}
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*ientry = env->utlb[utlb];
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update_itlb_use(env, itlb);
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return itlb;
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}
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/* Find itlb entry
|
2006-04-27 23:07:38 +02:00
|
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|
Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
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|
*/
|
2012-03-14 01:38:22 +01:00
|
|
|
static int find_itlb_entry(CPUSH4State * env, target_ulong address,
|
2011-01-09 23:53:45 +01:00
|
|
|
int use_asid)
|
2006-04-27 23:07:38 +02:00
|
|
|
{
|
2011-01-09 23:53:45 +01:00
|
|
|
int e;
|
2006-04-27 23:07:38 +02:00
|
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|
|
e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
|
2011-01-09 23:53:45 +01:00
|
|
|
if (e == MMU_DTLB_MULTIPLE) {
|
2006-04-27 23:07:38 +02:00
|
|
|
e = MMU_ITLB_MULTIPLE;
|
2011-01-09 23:53:45 +01:00
|
|
|
} else if (e == MMU_DTLB_MISS) {
|
2008-05-09 20:45:55 +02:00
|
|
|
e = MMU_ITLB_MISS;
|
2011-01-09 23:53:45 +01:00
|
|
|
} else if (e >= 0) {
|
2006-04-27 23:07:38 +02:00
|
|
|
update_itlb_use(env, e);
|
2011-01-09 23:53:45 +01:00
|
|
|
}
|
2006-04-27 23:07:38 +02:00
|
|
|
return e;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Find utlb entry
|
|
|
|
Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
|
2012-03-14 01:38:22 +01:00
|
|
|
static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid)
|
2006-04-27 23:07:38 +02:00
|
|
|
{
|
2008-08-22 10:57:43 +02:00
|
|
|
/* per utlb access */
|
|
|
|
increment_urc(env);
|
2006-04-27 23:07:38 +02:00
|
|
|
|
|
|
|
/* Return entry */
|
|
|
|
return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Match address against MMU
|
|
|
|
Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
|
|
|
|
MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
|
|
|
|
MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
|
2008-11-21 23:33:15 +01:00
|
|
|
MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
|
|
|
|
MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
|
2006-04-27 23:07:38 +02:00
|
|
|
*/
|
2012-03-14 01:38:22 +01:00
|
|
|
static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
|
2006-04-27 23:07:38 +02:00
|
|
|
int *prot, target_ulong address,
|
|
|
|
int rw, int access_type)
|
|
|
|
{
|
2008-11-21 23:33:15 +01:00
|
|
|
int use_asid, n;
|
2006-04-27 23:07:38 +02:00
|
|
|
tlb_t *matching = NULL;
|
|
|
|
|
2015-05-25 01:28:56 +02:00
|
|
|
use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD));
|
2006-04-27 23:07:38 +02:00
|
|
|
|
2008-11-21 23:33:15 +01:00
|
|
|
if (rw == 2) {
|
2011-01-09 23:53:45 +01:00
|
|
|
n = find_itlb_entry(env, address, use_asid);
|
2006-04-27 23:07:38 +02:00
|
|
|
if (n >= 0) {
|
|
|
|
matching = &env->itlb[n];
|
2015-05-25 01:28:56 +02:00
|
|
|
if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
|
2006-04-27 23:07:38 +02:00
|
|
|
n = MMU_ITLB_VIOLATION;
|
2015-05-25 01:28:56 +02:00
|
|
|
} else {
|
2010-02-02 22:32:14 +01:00
|
|
|
*prot = PAGE_EXEC;
|
2015-05-25 01:28:56 +02:00
|
|
|
}
|
2011-01-09 23:53:45 +01:00
|
|
|
} else {
|
|
|
|
n = find_utlb_entry(env, address, use_asid);
|
|
|
|
if (n >= 0) {
|
|
|
|
n = copy_utlb_entry_itlb(env, n);
|
|
|
|
matching = &env->itlb[n];
|
2015-05-25 01:28:56 +02:00
|
|
|
if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
|
|
|
|
n = MMU_ITLB_VIOLATION;
|
2011-01-09 23:53:45 +01:00
|
|
|
} else {
|
|
|
|
*prot = PAGE_READ | PAGE_EXEC;
|
|
|
|
if ((matching->pr & 1) && matching->d) {
|
|
|
|
*prot |= PAGE_WRITE;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else if (n == MMU_DTLB_MULTIPLE) {
|
|
|
|
n = MMU_ITLB_MULTIPLE;
|
|
|
|
} else if (n == MMU_DTLB_MISS) {
|
|
|
|
n = MMU_ITLB_MISS;
|
|
|
|
}
|
2006-04-27 23:07:38 +02:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
n = find_utlb_entry(env, address, use_asid);
|
|
|
|
if (n >= 0) {
|
|
|
|
matching = &env->utlb[n];
|
2015-05-25 01:28:56 +02:00
|
|
|
if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
|
2010-02-02 19:50:51 +01:00
|
|
|
n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
|
|
|
|
MMU_DTLB_VIOLATION_READ;
|
|
|
|
} else if ((rw == 1) && !(matching->pr & 1)) {
|
|
|
|
n = MMU_DTLB_VIOLATION_WRITE;
|
2011-01-15 13:50:38 +01:00
|
|
|
} else if ((rw == 1) && !matching->d) {
|
2010-02-02 19:50:51 +01:00
|
|
|
n = MMU_DTLB_INITIAL_WRITE;
|
|
|
|
} else {
|
|
|
|
*prot = PAGE_READ;
|
|
|
|
if ((matching->pr & 1) && matching->d) {
|
|
|
|
*prot |= PAGE_WRITE;
|
|
|
|
}
|
|
|
|
}
|
2006-04-27 23:07:38 +02:00
|
|
|
} else if (n == MMU_DTLB_MISS) {
|
2008-11-21 23:33:15 +01:00
|
|
|
n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
|
2006-04-27 23:07:38 +02:00
|
|
|
MMU_DTLB_MISS_READ;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (n >= 0) {
|
2010-02-02 19:50:51 +01:00
|
|
|
n = MMU_OK;
|
2006-04-27 23:07:38 +02:00
|
|
|
*physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
|
|
|
|
(address & (matching->size - 1));
|
|
|
|
}
|
|
|
|
return n;
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
static int get_physical_address(CPUSH4State * env, target_ulong * physical,
|
2009-03-03 07:12:03 +01:00
|
|
|
int *prot, target_ulong address,
|
|
|
|
int rw, int access_type)
|
2006-04-27 23:07:38 +02:00
|
|
|
{
|
|
|
|
/* P1, P2 and P4 areas do not use translation */
|
|
|
|
if ((address >= 0x80000000 && address < 0xc0000000) ||
|
|
|
|
address >= 0xe0000000) {
|
2015-05-25 01:28:56 +02:00
|
|
|
if (!(env->sr & (1u << SR_MD))
|
2010-02-03 18:02:55 +01:00
|
|
|
&& (address < 0xe0000000 || address >= 0xe4000000)) {
|
2006-04-27 23:07:38 +02:00
|
|
|
/* Unauthorized access in user mode (only store queues are available) */
|
2017-05-17 00:48:18 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "Unauthorized access\n");
|
2008-11-21 23:33:15 +01:00
|
|
|
if (rw == 0)
|
|
|
|
return MMU_DADDR_ERROR_READ;
|
|
|
|
else if (rw == 1)
|
|
|
|
return MMU_DADDR_ERROR_WRITE;
|
|
|
|
else
|
|
|
|
return MMU_IADDR_ERROR;
|
2006-04-27 23:07:38 +02:00
|
|
|
}
|
2008-08-22 10:57:43 +02:00
|
|
|
if (address >= 0x80000000 && address < 0xc0000000) {
|
|
|
|
/* Mask upper 3 bits for P1 and P2 areas */
|
|
|
|
*physical = address & 0x1fffffff;
|
|
|
|
} else {
|
|
|
|
*physical = address;
|
|
|
|
}
|
2010-02-02 22:32:14 +01:00
|
|
|
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
|
2006-04-27 23:07:38 +02:00
|
|
|
return MMU_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* If MMU is disabled, return the corresponding physical page */
|
2011-01-15 13:50:38 +01:00
|
|
|
if (!(env->mmucr & MMUCR_AT)) {
|
2006-04-27 23:07:38 +02:00
|
|
|
*physical = address & 0x1FFFFFFF;
|
2010-02-02 22:32:14 +01:00
|
|
|
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
|
2006-04-27 23:07:38 +02:00
|
|
|
return MMU_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* We need to resort to the MMU */
|
|
|
|
return get_mmu_address(env, physical, prot, address, rw, access_type);
|
|
|
|
}
|
|
|
|
|
2013-06-29 18:55:54 +02:00
|
|
|
hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
|
2006-06-17 21:58:25 +02:00
|
|
|
{
|
2013-06-29 18:55:54 +02:00
|
|
|
SuperHCPU *cpu = SUPERH_CPU(cs);
|
2006-06-17 21:58:25 +02:00
|
|
|
target_ulong physical;
|
|
|
|
int prot;
|
|
|
|
|
2013-06-29 18:55:54 +02:00
|
|
|
get_physical_address(&cpu->env, &physical, &prot, addr, 0, 0);
|
2006-06-17 21:58:25 +02:00
|
|
|
return physical;
|
|
|
|
}
|
|
|
|
|
2009-03-03 07:12:03 +01:00
|
|
|
void cpu_load_tlb(CPUSH4State * env)
|
2008-05-09 20:45:55 +02:00
|
|
|
{
|
2013-09-03 17:38:47 +02:00
|
|
|
SuperHCPU *cpu = sh_env_get_cpu(env);
|
2008-05-09 20:45:55 +02:00
|
|
|
int n = cpu_mmucr_urc(env->mmucr);
|
|
|
|
tlb_t * entry = &env->utlb[n];
|
|
|
|
|
2008-08-22 10:57:52 +02:00
|
|
|
if (entry->v) {
|
|
|
|
/* Overwriting valid entry in utlb. */
|
|
|
|
target_ulong address = entry->vpn << 10;
|
2013-09-04 01:29:02 +02:00
|
|
|
tlb_flush_page(CPU(cpu), address);
|
2008-08-22 10:57:52 +02:00
|
|
|
}
|
|
|
|
|
2008-05-09 20:45:55 +02:00
|
|
|
/* Take values into cpu status from registers. */
|
|
|
|
entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
|
|
|
|
entry->vpn = cpu_pteh_vpn(env->pteh);
|
|
|
|
entry->v = (uint8_t)cpu_ptel_v(env->ptel);
|
|
|
|
entry->ppn = cpu_ptel_ppn(env->ptel);
|
|
|
|
entry->sz = (uint8_t)cpu_ptel_sz(env->ptel);
|
|
|
|
switch (entry->sz) {
|
|
|
|
case 0: /* 00 */
|
|
|
|
entry->size = 1024; /* 1K */
|
|
|
|
break;
|
|
|
|
case 1: /* 01 */
|
|
|
|
entry->size = 1024 * 4; /* 4K */
|
|
|
|
break;
|
|
|
|
case 2: /* 10 */
|
|
|
|
entry->size = 1024 * 64; /* 64K */
|
|
|
|
break;
|
|
|
|
case 3: /* 11 */
|
|
|
|
entry->size = 1024 * 1024; /* 1M */
|
|
|
|
break;
|
|
|
|
default:
|
2013-09-03 17:38:47 +02:00
|
|
|
cpu_abort(CPU(cpu), "Unhandled load_tlb");
|
2008-05-09 20:45:55 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
entry->sh = (uint8_t)cpu_ptel_sh(env->ptel);
|
|
|
|
entry->c = (uint8_t)cpu_ptel_c(env->ptel);
|
|
|
|
entry->pr = (uint8_t)cpu_ptel_pr(env->ptel);
|
|
|
|
entry->d = (uint8_t)cpu_ptel_d(env->ptel);
|
|
|
|
entry->wt = (uint8_t)cpu_ptel_wt(env->ptel);
|
|
|
|
entry->sa = (uint8_t)cpu_ptea_sa(env->ptea);
|
|
|
|
entry->tc = (uint8_t)cpu_ptea_tc(env->ptea);
|
|
|
|
}
|
|
|
|
|
2010-02-02 19:39:11 +01:00
|
|
|
void cpu_sh4_invalidate_tlb(CPUSH4State *s)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* UTLB */
|
|
|
|
for (i = 0; i < UTLB_SIZE; i++) {
|
|
|
|
tlb_t * entry = &s->utlb[i];
|
|
|
|
entry->v = 0;
|
|
|
|
}
|
|
|
|
/* ITLB */
|
2011-01-25 07:32:01 +01:00
|
|
|
for (i = 0; i < ITLB_SIZE; i++) {
|
|
|
|
tlb_t * entry = &s->itlb[i];
|
2010-02-02 19:39:11 +01:00
|
|
|
entry->v = 0;
|
|
|
|
}
|
|
|
|
|
2016-11-14 15:17:28 +01:00
|
|
|
tlb_flush(CPU(sh_env_get_cpu(s)));
|
2010-02-02 19:39:11 +01:00
|
|
|
}
|
|
|
|
|
2011-01-26 02:16:39 +01:00
|
|
|
uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
|
2012-10-23 12:30:10 +02:00
|
|
|
hwaddr addr)
|
2011-01-26 02:16:39 +01:00
|
|
|
{
|
|
|
|
int index = (addr & 0x00000300) >> 8;
|
|
|
|
tlb_t * entry = &s->itlb[index];
|
|
|
|
|
|
|
|
return (entry->vpn << 10) |
|
|
|
|
(entry->v << 8) |
|
|
|
|
(entry->asid);
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
|
2011-01-09 23:53:45 +01:00
|
|
|
uint32_t mem_value)
|
|
|
|
{
|
|
|
|
uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
|
|
|
|
uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
|
|
|
|
uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
|
|
|
|
|
2011-01-26 02:07:50 +01:00
|
|
|
int index = (addr & 0x00000300) >> 8;
|
2011-01-09 23:53:45 +01:00
|
|
|
tlb_t * entry = &s->itlb[index];
|
|
|
|
if (entry->v) {
|
|
|
|
/* Overwriting valid entry in itlb. */
|
|
|
|
target_ulong address = entry->vpn << 10;
|
2013-09-04 01:29:02 +02:00
|
|
|
tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
|
2011-01-09 23:53:45 +01:00
|
|
|
}
|
|
|
|
entry->asid = asid;
|
|
|
|
entry->vpn = vpn;
|
|
|
|
entry->v = v;
|
|
|
|
}
|
|
|
|
|
2011-01-26 02:16:39 +01:00
|
|
|
uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
|
2012-10-23 12:30:10 +02:00
|
|
|
hwaddr addr)
|
2011-01-26 02:16:39 +01:00
|
|
|
{
|
|
|
|
int array = (addr & 0x00800000) >> 23;
|
|
|
|
int index = (addr & 0x00000300) >> 8;
|
|
|
|
tlb_t * entry = &s->itlb[index];
|
|
|
|
|
|
|
|
if (array == 0) {
|
|
|
|
/* ITLB Data Array 1 */
|
|
|
|
return (entry->ppn << 10) |
|
|
|
|
(entry->v << 8) |
|
|
|
|
(entry->pr << 5) |
|
|
|
|
((entry->sz & 1) << 6) |
|
|
|
|
((entry->sz & 2) << 4) |
|
|
|
|
(entry->c << 3) |
|
|
|
|
(entry->sh << 1);
|
|
|
|
} else {
|
|
|
|
/* ITLB Data Array 2 */
|
|
|
|
return (entry->tc << 1) |
|
|
|
|
(entry->sa);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
|
2011-01-26 02:07:50 +01:00
|
|
|
uint32_t mem_value)
|
|
|
|
{
|
|
|
|
int array = (addr & 0x00800000) >> 23;
|
|
|
|
int index = (addr & 0x00000300) >> 8;
|
|
|
|
tlb_t * entry = &s->itlb[index];
|
|
|
|
|
|
|
|
if (array == 0) {
|
|
|
|
/* ITLB Data Array 1 */
|
|
|
|
if (entry->v) {
|
|
|
|
/* Overwriting valid entry in utlb. */
|
|
|
|
target_ulong address = entry->vpn << 10;
|
2013-09-04 01:29:02 +02:00
|
|
|
tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
|
2011-01-26 02:07:50 +01:00
|
|
|
}
|
|
|
|
entry->ppn = (mem_value & 0x1ffffc00) >> 10;
|
|
|
|
entry->v = (mem_value & 0x00000100) >> 8;
|
|
|
|
entry->sz = (mem_value & 0x00000080) >> 6 |
|
|
|
|
(mem_value & 0x00000010) >> 4;
|
|
|
|
entry->pr = (mem_value & 0x00000040) >> 5;
|
|
|
|
entry->c = (mem_value & 0x00000008) >> 3;
|
|
|
|
entry->sh = (mem_value & 0x00000002) >> 1;
|
|
|
|
} else {
|
|
|
|
/* ITLB Data Array 2 */
|
|
|
|
entry->tc = (mem_value & 0x00000008) >> 3;
|
|
|
|
entry->sa = (mem_value & 0x00000007);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-01-26 02:16:39 +01:00
|
|
|
uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
|
2012-10-23 12:30:10 +02:00
|
|
|
hwaddr addr)
|
2011-01-26 02:16:39 +01:00
|
|
|
{
|
|
|
|
int index = (addr & 0x00003f00) >> 8;
|
|
|
|
tlb_t * entry = &s->utlb[index];
|
|
|
|
|
|
|
|
increment_urc(s); /* per utlb access */
|
|
|
|
|
|
|
|
return (entry->vpn << 10) |
|
|
|
|
(entry->v << 8) |
|
|
|
|
(entry->asid);
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
|
2008-08-22 10:57:43 +02:00
|
|
|
uint32_t mem_value)
|
|
|
|
{
|
|
|
|
int associate = addr & 0x0000080;
|
|
|
|
uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
|
|
|
|
uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
|
|
|
|
uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
|
|
|
|
uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
|
2015-05-25 01:28:56 +02:00
|
|
|
int use_asid = !(s->mmucr & MMUCR_SV) || !(s->sr & (1u << SR_MD));
|
2008-08-22 10:57:43 +02:00
|
|
|
|
|
|
|
if (associate) {
|
|
|
|
int i;
|
|
|
|
tlb_t * utlb_match_entry = NULL;
|
|
|
|
int needs_tlb_flush = 0;
|
|
|
|
|
|
|
|
/* search UTLB */
|
|
|
|
for (i = 0; i < UTLB_SIZE; i++) {
|
|
|
|
tlb_t * entry = &s->utlb[i];
|
|
|
|
if (!entry->v)
|
|
|
|
continue;
|
|
|
|
|
2008-12-10 18:31:51 +01:00
|
|
|
if (entry->vpn == vpn
|
|
|
|
&& (!use_asid || entry->asid == asid || entry->sh)) {
|
2008-08-22 10:57:43 +02:00
|
|
|
if (utlb_match_entry) {
|
2013-08-26 08:31:06 +02:00
|
|
|
CPUState *cs = CPU(sh_env_get_cpu(s));
|
|
|
|
|
2008-08-22 10:57:43 +02:00
|
|
|
/* Multiple TLB Exception */
|
2013-08-26 08:31:06 +02:00
|
|
|
cs->exception_index = 0x140;
|
2008-08-22 10:57:43 +02:00
|
|
|
s->tea = addr;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (entry->v && !v)
|
|
|
|
needs_tlb_flush = 1;
|
|
|
|
entry->v = v;
|
|
|
|
entry->d = d;
|
|
|
|
utlb_match_entry = entry;
|
|
|
|
}
|
|
|
|
increment_urc(s); /* per utlb access */
|
|
|
|
}
|
|
|
|
|
|
|
|
/* search ITLB */
|
|
|
|
for (i = 0; i < ITLB_SIZE; i++) {
|
|
|
|
tlb_t * entry = &s->itlb[i];
|
2008-12-10 18:31:51 +01:00
|
|
|
if (entry->vpn == vpn
|
|
|
|
&& (!use_asid || entry->asid == asid || entry->sh)) {
|
2008-08-22 10:57:43 +02:00
|
|
|
if (entry->v && !v)
|
|
|
|
needs_tlb_flush = 1;
|
|
|
|
if (utlb_match_entry)
|
|
|
|
*entry = *utlb_match_entry;
|
|
|
|
else
|
|
|
|
entry->v = v;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-09-04 01:29:02 +02:00
|
|
|
if (needs_tlb_flush) {
|
|
|
|
tlb_flush_page(CPU(sh_env_get_cpu(s)), vpn << 10);
|
|
|
|
}
|
2008-08-22 10:57:43 +02:00
|
|
|
} else {
|
|
|
|
int index = (addr & 0x00003f00) >> 8;
|
|
|
|
tlb_t * entry = &s->utlb[index];
|
|
|
|
if (entry->v) {
|
2013-09-04 01:29:02 +02:00
|
|
|
CPUState *cs = CPU(sh_env_get_cpu(s));
|
|
|
|
|
2008-08-22 10:57:43 +02:00
|
|
|
/* Overwriting valid entry in utlb. */
|
|
|
|
target_ulong address = entry->vpn << 10;
|
2013-09-04 01:29:02 +02:00
|
|
|
tlb_flush_page(cs, address);
|
2008-08-22 10:57:43 +02:00
|
|
|
}
|
|
|
|
entry->asid = asid;
|
|
|
|
entry->vpn = vpn;
|
|
|
|
entry->d = d;
|
|
|
|
entry->v = v;
|
|
|
|
increment_urc(s);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-01-26 02:16:39 +01:00
|
|
|
uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
|
2012-10-23 12:30:10 +02:00
|
|
|
hwaddr addr)
|
2011-01-26 02:16:39 +01:00
|
|
|
{
|
|
|
|
int array = (addr & 0x00800000) >> 23;
|
|
|
|
int index = (addr & 0x00003f00) >> 8;
|
|
|
|
tlb_t * entry = &s->utlb[index];
|
|
|
|
|
|
|
|
increment_urc(s); /* per utlb access */
|
|
|
|
|
|
|
|
if (array == 0) {
|
|
|
|
/* ITLB Data Array 1 */
|
|
|
|
return (entry->ppn << 10) |
|
|
|
|
(entry->v << 8) |
|
|
|
|
(entry->pr << 5) |
|
|
|
|
((entry->sz & 1) << 6) |
|
|
|
|
((entry->sz & 2) << 4) |
|
|
|
|
(entry->c << 3) |
|
|
|
|
(entry->d << 2) |
|
|
|
|
(entry->sh << 1) |
|
|
|
|
(entry->wt);
|
|
|
|
} else {
|
|
|
|
/* ITLB Data Array 2 */
|
|
|
|
return (entry->tc << 1) |
|
|
|
|
(entry->sa);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
|
2011-01-26 02:07:50 +01:00
|
|
|
uint32_t mem_value)
|
|
|
|
{
|
|
|
|
int array = (addr & 0x00800000) >> 23;
|
|
|
|
int index = (addr & 0x00003f00) >> 8;
|
|
|
|
tlb_t * entry = &s->utlb[index];
|
|
|
|
|
|
|
|
increment_urc(s); /* per utlb access */
|
|
|
|
|
|
|
|
if (array == 0) {
|
|
|
|
/* UTLB Data Array 1 */
|
|
|
|
if (entry->v) {
|
|
|
|
/* Overwriting valid entry in utlb. */
|
|
|
|
target_ulong address = entry->vpn << 10;
|
2013-09-04 01:29:02 +02:00
|
|
|
tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
|
2011-01-26 02:07:50 +01:00
|
|
|
}
|
|
|
|
entry->ppn = (mem_value & 0x1ffffc00) >> 10;
|
|
|
|
entry->v = (mem_value & 0x00000100) >> 8;
|
|
|
|
entry->sz = (mem_value & 0x00000080) >> 6 |
|
|
|
|
(mem_value & 0x00000010) >> 4;
|
|
|
|
entry->pr = (mem_value & 0x00000060) >> 5;
|
|
|
|
entry->c = (mem_value & 0x00000008) >> 3;
|
|
|
|
entry->d = (mem_value & 0x00000004) >> 2;
|
|
|
|
entry->sh = (mem_value & 0x00000002) >> 1;
|
|
|
|
entry->wt = (mem_value & 0x00000001);
|
|
|
|
} else {
|
|
|
|
/* UTLB Data Array 2 */
|
|
|
|
entry->tc = (mem_value & 0x00000008) >> 3;
|
|
|
|
entry->sa = (mem_value & 0x00000007);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-04-02 01:10:46 +02:00
|
|
|
int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
|
|
|
|
{
|
|
|
|
int n;
|
2015-05-25 01:28:56 +02:00
|
|
|
int use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD));
|
2009-04-02 01:10:46 +02:00
|
|
|
|
|
|
|
/* check area */
|
2015-05-25 01:28:56 +02:00
|
|
|
if (env->sr & (1u << SR_MD)) {
|
2015-09-08 23:45:14 +02:00
|
|
|
/* For privileged mode, P2 and P4 area is not cacheable. */
|
2009-04-02 01:10:46 +02:00
|
|
|
if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr)
|
|
|
|
return 0;
|
|
|
|
} else {
|
2015-09-08 23:45:14 +02:00
|
|
|
/* For user mode, only U0 area is cacheable. */
|
2009-04-02 01:10:46 +02:00
|
|
|
if (0x80000000 <= addr)
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* TODO : Evaluate CCR and check if the cache is on or off.
|
|
|
|
* Now CCR is not in CPUSH4State, but in SH7750State.
|
2011-11-22 11:06:21 +01:00
|
|
|
* When you move the ccr into CPUSH4State, the code will be
|
2009-04-02 01:10:46 +02:00
|
|
|
* as follows.
|
|
|
|
*/
|
|
|
|
#if 0
|
|
|
|
/* check if operand cache is enabled or not. */
|
|
|
|
if (!(env->ccr & 1))
|
|
|
|
return 0;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* if MMU is off, no check for TLB. */
|
|
|
|
if (env->mmucr & MMUCR_AT)
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
/* check TLB */
|
|
|
|
n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid);
|
|
|
|
if (n >= 0)
|
|
|
|
return env->itlb[n].c;
|
|
|
|
|
|
|
|
n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid);
|
|
|
|
if (n >= 0)
|
|
|
|
return env->utlb[n].c;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2006-06-17 21:58:25 +02:00
|
|
|
#endif
|
2014-09-13 18:45:23 +02:00
|
|
|
|
|
|
|
bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
|
|
|
|
{
|
|
|
|
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
2017-05-17 00:48:18 +02:00
|
|
|
SuperHCPU *cpu = SUPERH_CPU(cs);
|
|
|
|
CPUSH4State *env = &cpu->env;
|
|
|
|
|
|
|
|
/* Delay slots are indivisible, ignore interrupts */
|
|
|
|
if (env->flags & DELAY_SLOT_MASK) {
|
|
|
|
return false;
|
|
|
|
} else {
|
|
|
|
superh_cpu_do_interrupt(cs);
|
|
|
|
return true;
|
|
|
|
}
|
2014-09-13 18:45:23 +02:00
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
2019-04-02 17:18:39 +02:00
|
|
|
|
|
|
|
bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
|
|
|
|
MMUAccessType access_type, int mmu_idx,
|
|
|
|
bool probe, uintptr_t retaddr)
|
|
|
|
{
|
|
|
|
SuperHCPU *cpu = SUPERH_CPU(cs);
|
|
|
|
CPUSH4State *env = &cpu->env;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
#ifdef CONFIG_USER_ONLY
|
|
|
|
ret = (access_type == MMU_DATA_STORE ? MMU_DTLB_VIOLATION_WRITE :
|
|
|
|
access_type == MMU_INST_FETCH ? MMU_ITLB_VIOLATION :
|
|
|
|
MMU_DTLB_VIOLATION_READ);
|
|
|
|
#else
|
|
|
|
target_ulong physical;
|
|
|
|
int prot, sh_access_type;
|
|
|
|
|
|
|
|
sh_access_type = ACCESS_INT;
|
|
|
|
ret = get_physical_address(env, &physical, &prot, address,
|
|
|
|
access_type, sh_access_type);
|
|
|
|
|
|
|
|
if (ret == MMU_OK) {
|
|
|
|
address &= TARGET_PAGE_MASK;
|
|
|
|
physical &= TARGET_PAGE_MASK;
|
|
|
|
tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
if (probe) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) {
|
|
|
|
env->pteh = (env->pteh & PTEH_ASID_MASK) | (address & PTEH_VPN_MASK);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
env->tea = address;
|
|
|
|
switch (ret) {
|
|
|
|
case MMU_ITLB_MISS:
|
|
|
|
case MMU_DTLB_MISS_READ:
|
|
|
|
cs->exception_index = 0x040;
|
|
|
|
break;
|
|
|
|
case MMU_DTLB_MULTIPLE:
|
|
|
|
case MMU_ITLB_MULTIPLE:
|
|
|
|
cs->exception_index = 0x140;
|
|
|
|
break;
|
|
|
|
case MMU_ITLB_VIOLATION:
|
|
|
|
cs->exception_index = 0x0a0;
|
|
|
|
break;
|
|
|
|
case MMU_DTLB_MISS_WRITE:
|
|
|
|
cs->exception_index = 0x060;
|
|
|
|
break;
|
|
|
|
case MMU_DTLB_INITIAL_WRITE:
|
|
|
|
cs->exception_index = 0x080;
|
|
|
|
break;
|
|
|
|
case MMU_DTLB_VIOLATION_READ:
|
|
|
|
cs->exception_index = 0x0a0;
|
|
|
|
break;
|
|
|
|
case MMU_DTLB_VIOLATION_WRITE:
|
|
|
|
cs->exception_index = 0x0c0;
|
|
|
|
break;
|
|
|
|
case MMU_IADDR_ERROR:
|
|
|
|
case MMU_DADDR_ERROR_READ:
|
|
|
|
cs->exception_index = 0x0e0;
|
|
|
|
break;
|
|
|
|
case MMU_DADDR_ERROR_WRITE:
|
|
|
|
cs->exception_index = 0x100;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
cpu_abort(cs, "Unhandled MMU fault");
|
|
|
|
}
|
|
|
|
cpu_loop_exit_restore(cs, retaddr);
|
|
|
|
}
|