2018-04-24 21:26:16 +02:00
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/*
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* Emulation of Linux signals
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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2018-04-24 21:26:34 +02:00
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#include "qemu/osdep.h"
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#include "qemu.h"
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2021-09-08 17:44:03 +02:00
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#include "user-internals.h"
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2018-04-24 21:26:34 +02:00
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#include "signal-common.h"
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#include "linux-user/trace.h"
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/* Size of dummy stack frame allocated when calling signal handler.
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See arch/powerpc/include/asm/ptrace.h. */
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#if defined(TARGET_PPC64)
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#define SIGNAL_FRAMESIZE 128
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#else
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#define SIGNAL_FRAMESIZE 64
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#endif
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/* See arch/powerpc/include/asm/ucontext.h. Only used for 32-bit PPC;
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on 64-bit PPC, sigcontext and mcontext are one and the same. */
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struct target_mcontext {
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target_ulong mc_gregs[48];
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/* Includes fpscr. */
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uint64_t mc_fregs[33];
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2020-04-07 05:21:05 +02:00
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2018-04-24 21:26:34 +02:00
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#if defined(TARGET_PPC64)
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/* Pointer to the vector regs */
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target_ulong v_regs;
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2020-04-07 05:21:05 +02:00
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/*
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* On ppc64, this mcontext structure is naturally *unaligned*,
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* or rather it is aligned on a 8 bytes boundary but not on
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* a 16 byte boundary. This pad fixes it up. This is why we
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* cannot use ppc_avr_t, which would force alignment. This is
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* also why the vector regs are referenced in the ABI by the
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* v_regs pointer above so any amount of padding can be added here.
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*/
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target_ulong pad;
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/* VSCR and VRSAVE are saved separately. Also reserve space for VSX. */
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struct {
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uint64_t altivec[34 + 16][2];
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} mc_vregs;
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2018-04-24 21:26:34 +02:00
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#else
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target_ulong mc_pad[2];
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2020-04-07 05:21:05 +02:00
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2018-04-24 21:26:34 +02:00
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/* We need to handle Altivec and SPE at the same time, which no
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kernel needs to do. Fortunately, the kernel defines this bit to
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be Altivec-register-large all the time, rather than trying to
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twiddle it based on the specific platform. */
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union {
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/* SPE vector registers. One extra for SPEFSCR. */
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uint32_t spe[33];
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2020-04-07 05:21:05 +02:00
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/*
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* Altivec vector registers. One extra for VRSAVE.
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* On ppc32, we are already aligned to 16 bytes. We could
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* use ppc_avr_t, but choose to share the same type as ppc64.
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2018-04-24 21:26:34 +02:00
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*/
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2020-04-07 05:21:05 +02:00
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uint64_t altivec[33][2];
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2018-04-24 21:26:34 +02:00
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} mc_vregs;
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2020-04-07 05:21:05 +02:00
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#endif
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2018-04-24 21:26:34 +02:00
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};
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/* See arch/powerpc/include/asm/sigcontext.h. */
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struct target_sigcontext {
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target_ulong _unused[4];
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int32_t signal;
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#if defined(TARGET_PPC64)
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int32_t pad0;
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#endif
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target_ulong handler;
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target_ulong oldmask;
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target_ulong regs; /* struct pt_regs __user * */
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#if defined(TARGET_PPC64)
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struct target_mcontext mcontext;
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#endif
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};
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/* Indices for target_mcontext.mc_gregs, below.
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See arch/powerpc/include/asm/ptrace.h for details. */
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enum {
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TARGET_PT_R0 = 0,
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TARGET_PT_R1 = 1,
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TARGET_PT_R2 = 2,
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TARGET_PT_R3 = 3,
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TARGET_PT_R4 = 4,
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TARGET_PT_R5 = 5,
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TARGET_PT_R6 = 6,
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TARGET_PT_R7 = 7,
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TARGET_PT_R8 = 8,
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TARGET_PT_R9 = 9,
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TARGET_PT_R10 = 10,
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TARGET_PT_R11 = 11,
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TARGET_PT_R12 = 12,
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TARGET_PT_R13 = 13,
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TARGET_PT_R14 = 14,
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TARGET_PT_R15 = 15,
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TARGET_PT_R16 = 16,
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TARGET_PT_R17 = 17,
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TARGET_PT_R18 = 18,
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TARGET_PT_R19 = 19,
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TARGET_PT_R20 = 20,
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TARGET_PT_R21 = 21,
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TARGET_PT_R22 = 22,
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TARGET_PT_R23 = 23,
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TARGET_PT_R24 = 24,
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TARGET_PT_R25 = 25,
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TARGET_PT_R26 = 26,
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TARGET_PT_R27 = 27,
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TARGET_PT_R28 = 28,
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TARGET_PT_R29 = 29,
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TARGET_PT_R30 = 30,
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TARGET_PT_R31 = 31,
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TARGET_PT_NIP = 32,
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TARGET_PT_MSR = 33,
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TARGET_PT_ORIG_R3 = 34,
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TARGET_PT_CTR = 35,
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TARGET_PT_LNK = 36,
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TARGET_PT_XER = 37,
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TARGET_PT_CCR = 38,
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/* Yes, there are two registers with #39. One is 64-bit only. */
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TARGET_PT_MQ = 39,
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TARGET_PT_SOFTE = 39,
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TARGET_PT_TRAP = 40,
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TARGET_PT_DAR = 41,
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TARGET_PT_DSISR = 42,
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TARGET_PT_RESULT = 43,
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TARGET_PT_REGS_COUNT = 44
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};
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struct target_ucontext {
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target_ulong tuc_flags;
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target_ulong tuc_link; /* ucontext_t __user * */
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struct target_sigaltstack tuc_stack;
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#if !defined(TARGET_PPC64)
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int32_t tuc_pad[7];
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target_ulong tuc_regs; /* struct mcontext __user *
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points to uc_mcontext field */
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#endif
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target_sigset_t tuc_sigmask;
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#if defined(TARGET_PPC64)
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target_sigset_t unused[15]; /* Allow for uc_sigmask growth */
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struct target_sigcontext tuc_sigcontext;
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#else
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int32_t tuc_maskext[30];
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int32_t tuc_pad2[3];
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struct target_mcontext tuc_mcontext;
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#endif
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};
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/* See arch/powerpc/kernel/signal_32.c. */
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struct target_sigframe {
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struct target_sigcontext sctx;
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struct target_mcontext mctx;
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int32_t abigap[56];
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};
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#if defined(TARGET_PPC64)
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#define TARGET_TRAMP_SIZE 6
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struct target_rt_sigframe {
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/* sys_rt_sigreturn requires the ucontext be the first field */
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struct target_ucontext uc;
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target_ulong _unused[2];
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uint32_t trampoline[TARGET_TRAMP_SIZE];
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target_ulong pinfo; /* struct siginfo __user * */
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target_ulong puc; /* void __user * */
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struct target_siginfo info;
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/* 64 bit ABI allows for 288 bytes below sp before decrementing it. */
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char abigap[288];
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} __attribute__((aligned(16)));
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#else
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struct target_rt_sigframe {
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struct target_siginfo info;
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struct target_ucontext uc;
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int32_t abigap[56];
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};
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#endif
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#if defined(TARGET_PPC64)
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struct target_func_ptr {
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target_ulong entry;
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target_ulong toc;
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};
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#endif
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/* See arch/powerpc/kernel/signal.c. */
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static target_ulong get_sigframe(struct target_sigaction *ka,
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CPUPPCState *env,
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int frame_size)
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{
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target_ulong oldsp;
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2018-04-11 21:23:47 +02:00
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oldsp = target_sigsp(get_sp_from_cpustate(env), ka);
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2018-04-24 21:26:34 +02:00
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return (oldsp - frame_size) & ~0xFUL;
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}
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#if ((defined(TARGET_WORDS_BIGENDIAN) && defined(HOST_WORDS_BIGENDIAN)) || \
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(!defined(HOST_WORDS_BIGENDIAN) && !defined(TARGET_WORDS_BIGENDIAN)))
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#define PPC_VEC_HI 0
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#define PPC_VEC_LO 1
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#else
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#define PPC_VEC_HI 1
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#define PPC_VEC_LO 0
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#endif
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static void save_user_regs(CPUPPCState *env, struct target_mcontext *frame)
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{
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target_ulong msr = env->msr;
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int i;
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target_ulong ccr = 0;
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/* In general, the kernel attempts to be intelligent about what it
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needs to save for Altivec/FP/SPE registers. We don't care that
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much, so we just go ahead and save everything. */
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/* Save general registers. */
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for (i = 0; i < ARRAY_SIZE(env->gpr); i++) {
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__put_user(env->gpr[i], &frame->mc_gregs[i]);
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}
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__put_user(env->nip, &frame->mc_gregs[TARGET_PT_NIP]);
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__put_user(env->ctr, &frame->mc_gregs[TARGET_PT_CTR]);
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__put_user(env->lr, &frame->mc_gregs[TARGET_PT_LNK]);
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__put_user(env->xer, &frame->mc_gregs[TARGET_PT_XER]);
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for (i = 0; i < ARRAY_SIZE(env->crf); i++) {
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ccr |= env->crf[i] << (32 - ((i + 1) * 4));
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}
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__put_user(ccr, &frame->mc_gregs[TARGET_PT_CCR]);
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/* Save Altivec registers if necessary. */
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if (env->insns_flags & PPC_ALTIVEC) {
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uint32_t *vrsave;
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2019-01-02 10:14:22 +01:00
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for (i = 0; i < 32; i++) {
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ppc_avr_t *avr = cpu_avr_ptr(env, i);
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2018-04-24 21:26:34 +02:00
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ppc_avr_t *vreg = (ppc_avr_t *)&frame->mc_vregs.altivec[i];
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__put_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]);
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__put_user(avr->u64[PPC_VEC_LO], &vreg->u64[1]);
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}
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#if defined(TARGET_PPC64)
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vrsave = (uint32_t *)&frame->mc_vregs.altivec[33];
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/* 64-bit needs to put a pointer to the vectors in the frame */
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__put_user(h2g(frame->mc_vregs.altivec), &frame->v_regs);
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#else
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vrsave = (uint32_t *)&frame->mc_vregs.altivec[32];
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#endif
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__put_user((uint32_t)env->spr[SPR_VRSAVE], vrsave);
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}
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2020-04-07 05:21:05 +02:00
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#if defined(TARGET_PPC64)
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2018-04-24 21:26:34 +02:00
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/* Save VSX second halves */
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if (env->insns_flags2 & PPC2_VSX) {
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uint64_t *vsregs = (uint64_t *)&frame->mc_vregs.altivec[34];
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2019-01-02 10:14:22 +01:00
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for (i = 0; i < 32; i++) {
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uint64_t *vsrl = cpu_vsrl_ptr(env, i);
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__put_user(*vsrl, &vsregs[i]);
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2018-04-24 21:26:34 +02:00
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}
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}
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2020-04-07 05:21:05 +02:00
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#endif
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2018-04-24 21:26:34 +02:00
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/* Save floating point registers. */
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if (env->insns_flags & PPC_FLOAT) {
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2019-01-02 10:14:22 +01:00
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for (i = 0; i < 32; i++) {
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uint64_t *fpr = cpu_fpr_ptr(env, i);
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__put_user(*fpr, &frame->mc_fregs[i]);
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2018-04-24 21:26:34 +02:00
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}
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__put_user((uint64_t) env->fpscr, &frame->mc_fregs[32]);
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}
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2020-04-07 05:21:05 +02:00
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#if !defined(TARGET_PPC64)
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2018-04-24 21:26:34 +02:00
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/* Save SPE registers. The kernel only saves the high half. */
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if (env->insns_flags & PPC_SPE) {
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for (i = 0; i < ARRAY_SIZE(env->gprh); i++) {
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__put_user(env->gprh[i], &frame->mc_vregs.spe[i]);
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}
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__put_user(env->spe_fscr, &frame->mc_vregs.spe[32]);
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}
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2020-04-07 05:21:05 +02:00
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#endif
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2018-04-24 21:26:34 +02:00
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/* Store MSR. */
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__put_user(msr, &frame->mc_gregs[TARGET_PT_MSR]);
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}
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static void encode_trampoline(int sigret, uint32_t *tramp)
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{
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/* Set up the sigreturn trampoline: li r0,sigret; sc. */
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2021-09-29 15:05:45 +02:00
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__put_user(0x38000000 | sigret, &tramp[0]);
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__put_user(0x44000002, &tramp[1]);
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2018-04-24 21:26:34 +02:00
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}
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static void restore_user_regs(CPUPPCState *env,
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struct target_mcontext *frame, int sig)
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{
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target_ulong save_r2 = 0;
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target_ulong msr;
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target_ulong ccr;
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int i;
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if (!sig) {
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save_r2 = env->gpr[2];
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}
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/* Restore general registers. */
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for (i = 0; i < ARRAY_SIZE(env->gpr); i++) {
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__get_user(env->gpr[i], &frame->mc_gregs[i]);
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}
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__get_user(env->nip, &frame->mc_gregs[TARGET_PT_NIP]);
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|
|
__get_user(env->ctr, &frame->mc_gregs[TARGET_PT_CTR]);
|
|
|
|
__get_user(env->lr, &frame->mc_gregs[TARGET_PT_LNK]);
|
|
|
|
__get_user(env->xer, &frame->mc_gregs[TARGET_PT_XER]);
|
|
|
|
__get_user(ccr, &frame->mc_gregs[TARGET_PT_CCR]);
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(env->crf); i++) {
|
|
|
|
env->crf[i] = (ccr >> (32 - ((i + 1) * 4))) & 0xf;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!sig) {
|
|
|
|
env->gpr[2] = save_r2;
|
|
|
|
}
|
|
|
|
/* Restore MSR. */
|
|
|
|
__get_user(msr, &frame->mc_gregs[TARGET_PT_MSR]);
|
|
|
|
|
|
|
|
/* If doing signal return, restore the previous little-endian mode. */
|
2021-03-23 19:43:39 +01:00
|
|
|
if (sig) {
|
|
|
|
ppc_store_msr(env, ((env->msr & ~(1ull << MSR_LE)) |
|
|
|
|
(msr & (1ull << MSR_LE))));
|
|
|
|
}
|
2018-04-24 21:26:34 +02:00
|
|
|
|
|
|
|
/* Restore Altivec registers if necessary. */
|
|
|
|
if (env->insns_flags & PPC_ALTIVEC) {
|
|
|
|
ppc_avr_t *v_regs;
|
|
|
|
uint32_t *vrsave;
|
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
uint64_t v_addr;
|
|
|
|
/* 64-bit needs to recover the pointer to the vectors from the frame */
|
|
|
|
__get_user(v_addr, &frame->v_regs);
|
2021-02-12 19:48:43 +01:00
|
|
|
v_regs = g2h(env_cpu(env), v_addr);
|
2018-04-24 21:26:34 +02:00
|
|
|
#else
|
|
|
|
v_regs = (ppc_avr_t *)frame->mc_vregs.altivec;
|
|
|
|
#endif
|
2019-01-02 10:14:22 +01:00
|
|
|
for (i = 0; i < 32; i++) {
|
|
|
|
ppc_avr_t *avr = cpu_avr_ptr(env, i);
|
2018-04-24 21:26:34 +02:00
|
|
|
ppc_avr_t *vreg = &v_regs[i];
|
|
|
|
|
|
|
|
__get_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]);
|
|
|
|
__get_user(avr->u64[PPC_VEC_LO], &vreg->u64[1]);
|
|
|
|
}
|
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
vrsave = (uint32_t *)&v_regs[33];
|
|
|
|
#else
|
|
|
|
vrsave = (uint32_t *)&v_regs[32];
|
|
|
|
#endif
|
|
|
|
__get_user(env->spr[SPR_VRSAVE], vrsave);
|
|
|
|
}
|
|
|
|
|
2020-04-07 05:21:05 +02:00
|
|
|
#if defined(TARGET_PPC64)
|
2018-04-24 21:26:34 +02:00
|
|
|
/* Restore VSX second halves */
|
|
|
|
if (env->insns_flags2 & PPC2_VSX) {
|
|
|
|
uint64_t *vsregs = (uint64_t *)&frame->mc_vregs.altivec[34];
|
2019-01-02 10:14:22 +01:00
|
|
|
for (i = 0; i < 32; i++) {
|
|
|
|
uint64_t *vsrl = cpu_vsrl_ptr(env, i);
|
|
|
|
__get_user(*vsrl, &vsregs[i]);
|
2018-04-24 21:26:34 +02:00
|
|
|
}
|
|
|
|
}
|
2020-04-07 05:21:05 +02:00
|
|
|
#endif
|
2018-04-24 21:26:34 +02:00
|
|
|
|
|
|
|
/* Restore floating point registers. */
|
|
|
|
if (env->insns_flags & PPC_FLOAT) {
|
|
|
|
uint64_t fpscr;
|
2019-01-02 10:14:22 +01:00
|
|
|
for (i = 0; i < 32; i++) {
|
|
|
|
uint64_t *fpr = cpu_fpr_ptr(env, i);
|
|
|
|
__get_user(*fpr, &frame->mc_fregs[i]);
|
2018-04-24 21:26:34 +02:00
|
|
|
}
|
|
|
|
__get_user(fpscr, &frame->mc_fregs[32]);
|
|
|
|
env->fpscr = (uint32_t) fpscr;
|
|
|
|
}
|
|
|
|
|
2020-04-07 05:21:05 +02:00
|
|
|
#if !defined(TARGET_PPC64)
|
2018-04-24 21:26:34 +02:00
|
|
|
/* Save SPE registers. The kernel only saves the high half. */
|
|
|
|
if (env->insns_flags & PPC_SPE) {
|
|
|
|
for (i = 0; i < ARRAY_SIZE(env->gprh); i++) {
|
|
|
|
__get_user(env->gprh[i], &frame->mc_vregs.spe[i]);
|
|
|
|
}
|
|
|
|
__get_user(env->spe_fscr, &frame->mc_vregs.spe[32]);
|
|
|
|
}
|
2020-04-07 05:21:05 +02:00
|
|
|
#endif
|
2018-04-24 21:26:34 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
#if !defined(TARGET_PPC64)
|
|
|
|
void setup_frame(int sig, struct target_sigaction *ka,
|
|
|
|
target_sigset_t *set, CPUPPCState *env)
|
|
|
|
{
|
|
|
|
struct target_sigframe *frame;
|
|
|
|
struct target_sigcontext *sc;
|
|
|
|
target_ulong frame_addr, newsp;
|
|
|
|
int err = 0;
|
|
|
|
|
|
|
|
frame_addr = get_sigframe(ka, env, sizeof(*frame));
|
|
|
|
trace_user_setup_frame(env, frame_addr);
|
|
|
|
if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 1))
|
|
|
|
goto sigsegv;
|
|
|
|
sc = &frame->sctx;
|
|
|
|
|
|
|
|
__put_user(ka->_sa_handler, &sc->handler);
|
|
|
|
__put_user(set->sig[0], &sc->oldmask);
|
|
|
|
__put_user(set->sig[1], &sc->_unused[3]);
|
|
|
|
__put_user(h2g(&frame->mctx), &sc->regs);
|
|
|
|
__put_user(sig, &sc->signal);
|
|
|
|
|
|
|
|
/* Save user regs. */
|
|
|
|
save_user_regs(env, &frame->mctx);
|
|
|
|
|
2021-09-29 15:05:46 +02:00
|
|
|
env->lr = default_sigreturn;
|
2018-04-24 21:26:34 +02:00
|
|
|
|
|
|
|
/* Turn off all fp exceptions. */
|
|
|
|
env->fpscr = 0;
|
|
|
|
|
|
|
|
/* Create a stack frame for the caller of the handler. */
|
|
|
|
newsp = frame_addr - SIGNAL_FRAMESIZE;
|
|
|
|
err |= put_user(env->gpr[1], newsp, target_ulong);
|
|
|
|
|
|
|
|
if (err)
|
|
|
|
goto sigsegv;
|
|
|
|
|
|
|
|
/* Set up registers for signal handler. */
|
|
|
|
env->gpr[1] = newsp;
|
|
|
|
env->gpr[3] = sig;
|
|
|
|
env->gpr[4] = frame_addr + offsetof(struct target_sigframe, sctx);
|
|
|
|
|
|
|
|
env->nip = (target_ulong) ka->_sa_handler;
|
|
|
|
|
|
|
|
/* Signal handlers are entered in big-endian mode. */
|
2021-03-23 19:43:39 +01:00
|
|
|
ppc_store_msr(env, env->msr & ~(1ull << MSR_LE));
|
2018-04-24 21:26:34 +02:00
|
|
|
|
|
|
|
unlock_user_struct(frame, frame_addr, 1);
|
|
|
|
return;
|
|
|
|
|
|
|
|
sigsegv:
|
|
|
|
unlock_user_struct(frame, frame_addr, 1);
|
|
|
|
force_sigsegv(sig);
|
|
|
|
}
|
|
|
|
#endif /* !defined(TARGET_PPC64) */
|
|
|
|
|
|
|
|
void setup_rt_frame(int sig, struct target_sigaction *ka,
|
|
|
|
target_siginfo_t *info,
|
|
|
|
target_sigset_t *set, CPUPPCState *env)
|
|
|
|
{
|
|
|
|
struct target_rt_sigframe *rt_sf;
|
|
|
|
struct target_mcontext *mctx = 0;
|
|
|
|
target_ulong rt_sf_addr, newsp = 0;
|
|
|
|
int i, err = 0;
|
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
struct target_sigcontext *sc = 0;
|
2019-09-11 11:37:43 +02:00
|
|
|
#if !defined(TARGET_ABI32)
|
2018-04-24 21:26:34 +02:00
|
|
|
struct image_info *image = ((TaskState *)thread_cpu->opaque)->info;
|
2019-09-11 11:37:43 +02:00
|
|
|
#endif
|
2018-04-24 21:26:34 +02:00
|
|
|
#endif
|
|
|
|
|
|
|
|
rt_sf_addr = get_sigframe(ka, env, sizeof(*rt_sf));
|
|
|
|
if (!lock_user_struct(VERIFY_WRITE, rt_sf, rt_sf_addr, 1))
|
|
|
|
goto sigsegv;
|
|
|
|
|
|
|
|
tswap_siginfo(&rt_sf->info, info);
|
|
|
|
|
|
|
|
__put_user(0, &rt_sf->uc.tuc_flags);
|
|
|
|
__put_user(0, &rt_sf->uc.tuc_link);
|
2018-04-11 21:23:47 +02:00
|
|
|
target_save_altstack(&rt_sf->uc.tuc_stack, env);
|
2018-04-24 21:26:34 +02:00
|
|
|
#if !defined(TARGET_PPC64)
|
|
|
|
__put_user(h2g (&rt_sf->uc.tuc_mcontext),
|
|
|
|
&rt_sf->uc.tuc_regs);
|
|
|
|
#endif
|
|
|
|
for(i = 0; i < TARGET_NSIG_WORDS; i++) {
|
|
|
|
__put_user(set->sig[i], &rt_sf->uc.tuc_sigmask.sig[i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
mctx = &rt_sf->uc.tuc_sigcontext.mcontext;
|
|
|
|
|
|
|
|
sc = &rt_sf->uc.tuc_sigcontext;
|
|
|
|
__put_user(h2g(mctx), &sc->regs);
|
|
|
|
__put_user(sig, &sc->signal);
|
|
|
|
#else
|
|
|
|
mctx = &rt_sf->uc.tuc_mcontext;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
save_user_regs(env, mctx);
|
|
|
|
|
2021-09-29 15:05:46 +02:00
|
|
|
env->lr = default_rt_sigreturn;
|
2018-04-24 21:26:34 +02:00
|
|
|
|
|
|
|
/* Turn off all fp exceptions. */
|
|
|
|
env->fpscr = 0;
|
|
|
|
|
|
|
|
/* Create a stack frame for the caller of the handler. */
|
|
|
|
newsp = rt_sf_addr - (SIGNAL_FRAMESIZE + 16);
|
|
|
|
err |= put_user(env->gpr[1], newsp, target_ulong);
|
|
|
|
|
|
|
|
if (err)
|
|
|
|
goto sigsegv;
|
|
|
|
|
|
|
|
/* Set up registers for signal handler. */
|
|
|
|
env->gpr[1] = newsp;
|
|
|
|
env->gpr[3] = (target_ulong) sig;
|
|
|
|
env->gpr[4] = (target_ulong) h2g(&rt_sf->info);
|
|
|
|
env->gpr[5] = (target_ulong) h2g(&rt_sf->uc);
|
|
|
|
env->gpr[6] = (target_ulong) h2g(rt_sf);
|
|
|
|
|
2019-09-11 11:37:43 +02:00
|
|
|
#if defined(TARGET_PPC64) && !defined(TARGET_ABI32)
|
2018-04-24 21:26:34 +02:00
|
|
|
if (get_ppc64_abi(image) < 2) {
|
|
|
|
/* ELFv1 PPC64 function pointers are pointers to OPD entries. */
|
|
|
|
struct target_func_ptr *handler =
|
2021-02-12 19:48:43 +01:00
|
|
|
(struct target_func_ptr *)g2h(env_cpu(env), ka->_sa_handler);
|
2018-04-24 21:26:34 +02:00
|
|
|
env->nip = tswapl(handler->entry);
|
|
|
|
env->gpr[2] = tswapl(handler->toc);
|
|
|
|
} else {
|
2020-03-19 14:32:44 +01:00
|
|
|
/* ELFv2 PPC64 function pointers are entry points. R12 must also be set. */
|
|
|
|
env->gpr[12] = env->nip = ka->_sa_handler;
|
2018-04-24 21:26:34 +02:00
|
|
|
}
|
|
|
|
#else
|
|
|
|
env->nip = (target_ulong) ka->_sa_handler;
|
|
|
|
#endif
|
|
|
|
|
2021-03-23 19:43:39 +01:00
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
2018-04-24 21:26:34 +02:00
|
|
|
/* Signal handlers are entered in big-endian mode. */
|
2021-03-23 19:43:39 +01:00
|
|
|
ppc_store_msr(env, env->msr & ~(1ull << MSR_LE));
|
|
|
|
#else
|
|
|
|
/* Signal handlers are entered in little-endian mode. */
|
|
|
|
ppc_store_msr(env, env->msr | (1ull << MSR_LE));
|
|
|
|
#endif
|
2018-04-24 21:26:34 +02:00
|
|
|
|
|
|
|
unlock_user_struct(rt_sf, rt_sf_addr, 1);
|
|
|
|
return;
|
|
|
|
|
|
|
|
sigsegv:
|
|
|
|
unlock_user_struct(rt_sf, rt_sf_addr, 1);
|
|
|
|
force_sigsegv(sig);
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2020-03-10 11:33:51 +01:00
|
|
|
#if !defined(TARGET_PPC64) || defined(TARGET_ABI32)
|
2018-04-24 21:26:34 +02:00
|
|
|
long do_sigreturn(CPUPPCState *env)
|
|
|
|
{
|
|
|
|
struct target_sigcontext *sc = NULL;
|
|
|
|
struct target_mcontext *sr = NULL;
|
|
|
|
target_ulong sr_addr = 0, sc_addr;
|
|
|
|
sigset_t blocked;
|
|
|
|
target_sigset_t set;
|
|
|
|
|
|
|
|
sc_addr = env->gpr[1] + SIGNAL_FRAMESIZE;
|
|
|
|
if (!lock_user_struct(VERIFY_READ, sc, sc_addr, 1))
|
|
|
|
goto sigsegv;
|
|
|
|
|
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
set.sig[0] = sc->oldmask + ((uint64_t)(sc->_unused[3]) << 32);
|
|
|
|
#else
|
|
|
|
__get_user(set.sig[0], &sc->oldmask);
|
|
|
|
__get_user(set.sig[1], &sc->_unused[3]);
|
|
|
|
#endif
|
|
|
|
target_to_host_sigset_internal(&blocked, &set);
|
|
|
|
set_sigmask(&blocked);
|
|
|
|
|
|
|
|
__get_user(sr_addr, &sc->regs);
|
|
|
|
if (!lock_user_struct(VERIFY_READ, sr, sr_addr, 1))
|
|
|
|
goto sigsegv;
|
|
|
|
restore_user_regs(env, sr, 1);
|
|
|
|
|
|
|
|
unlock_user_struct(sr, sr_addr, 1);
|
|
|
|
unlock_user_struct(sc, sc_addr, 1);
|
|
|
|
return -TARGET_QEMU_ESIGRETURN;
|
|
|
|
|
|
|
|
sigsegv:
|
|
|
|
unlock_user_struct(sr, sr_addr, 1);
|
|
|
|
unlock_user_struct(sc, sc_addr, 1);
|
|
|
|
force_sig(TARGET_SIGSEGV);
|
|
|
|
return -TARGET_QEMU_ESIGRETURN;
|
|
|
|
}
|
|
|
|
#endif /* !defined(TARGET_PPC64) */
|
|
|
|
|
|
|
|
/* See arch/powerpc/kernel/signal_32.c. */
|
|
|
|
static int do_setcontext(struct target_ucontext *ucp, CPUPPCState *env, int sig)
|
|
|
|
{
|
|
|
|
struct target_mcontext *mcp;
|
|
|
|
target_ulong mcp_addr;
|
|
|
|
sigset_t blocked;
|
|
|
|
target_sigset_t set;
|
|
|
|
|
|
|
|
if (copy_from_user(&set, h2g(ucp) + offsetof(struct target_ucontext, tuc_sigmask),
|
|
|
|
sizeof (set)))
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
mcp_addr = h2g(ucp) +
|
|
|
|
offsetof(struct target_ucontext, tuc_sigcontext.mcontext);
|
|
|
|
#else
|
|
|
|
__get_user(mcp_addr, &ucp->tuc_regs);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
if (!lock_user_struct(VERIFY_READ, mcp, mcp_addr, 1))
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
target_to_host_sigset_internal(&blocked, &set);
|
|
|
|
set_sigmask(&blocked);
|
|
|
|
restore_user_regs(env, mcp, sig);
|
|
|
|
|
|
|
|
unlock_user_struct(mcp, mcp_addr, 1);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
long do_rt_sigreturn(CPUPPCState *env)
|
|
|
|
{
|
|
|
|
struct target_rt_sigframe *rt_sf = NULL;
|
|
|
|
target_ulong rt_sf_addr;
|
|
|
|
|
|
|
|
rt_sf_addr = env->gpr[1] + SIGNAL_FRAMESIZE + 16;
|
|
|
|
if (!lock_user_struct(VERIFY_READ, rt_sf, rt_sf_addr, 1))
|
|
|
|
goto sigsegv;
|
|
|
|
|
|
|
|
if (do_setcontext(&rt_sf->uc, env, 1))
|
|
|
|
goto sigsegv;
|
|
|
|
|
2021-04-26 04:53:13 +02:00
|
|
|
target_restore_altstack(&rt_sf->uc.tuc_stack, env);
|
2018-04-24 21:26:34 +02:00
|
|
|
|
|
|
|
unlock_user_struct(rt_sf, rt_sf_addr, 1);
|
|
|
|
return -TARGET_QEMU_ESIGRETURN;
|
|
|
|
|
|
|
|
sigsegv:
|
|
|
|
unlock_user_struct(rt_sf, rt_sf_addr, 1);
|
|
|
|
force_sig(TARGET_SIGSEGV);
|
|
|
|
return -TARGET_QEMU_ESIGRETURN;
|
|
|
|
}
|
2018-07-18 22:06:48 +02:00
|
|
|
|
|
|
|
/* This syscall implements {get,set,swap}context for userland. */
|
|
|
|
abi_long do_swapcontext(CPUArchState *env, abi_ulong uold_ctx,
|
|
|
|
abi_ulong unew_ctx, abi_long ctx_size)
|
|
|
|
{
|
|
|
|
struct target_ucontext *uctx;
|
|
|
|
struct target_mcontext *mctx;
|
|
|
|
|
|
|
|
/* For ppc32, ctx_size is "reserved for future use".
|
|
|
|
* For ppc64, we do not yet support the VSX extension.
|
|
|
|
*/
|
|
|
|
if (ctx_size < sizeof(struct target_ucontext)) {
|
|
|
|
return -TARGET_EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (uold_ctx) {
|
|
|
|
TaskState *ts = (TaskState *)thread_cpu->opaque;
|
|
|
|
|
|
|
|
if (!lock_user_struct(VERIFY_WRITE, uctx, uold_ctx, 1)) {
|
|
|
|
return -TARGET_EFAULT;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef TARGET_PPC64
|
|
|
|
mctx = &uctx->tuc_sigcontext.mcontext;
|
|
|
|
#else
|
|
|
|
/* ??? The kernel aligns the pointer down here into padding, but
|
|
|
|
* in setup_rt_frame we don't. Be self-compatible for now.
|
|
|
|
*/
|
|
|
|
mctx = &uctx->tuc_mcontext;
|
|
|
|
__put_user(h2g(mctx), &uctx->tuc_regs);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
save_user_regs(env, mctx);
|
|
|
|
host_to_target_sigset(&uctx->tuc_sigmask, &ts->signal_mask);
|
|
|
|
|
|
|
|
unlock_user_struct(uctx, uold_ctx, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (unew_ctx) {
|
|
|
|
int err;
|
|
|
|
|
|
|
|
if (!lock_user_struct(VERIFY_READ, uctx, unew_ctx, 1)) {
|
|
|
|
return -TARGET_EFAULT;
|
|
|
|
}
|
|
|
|
err = do_setcontext(uctx, env, 0);
|
|
|
|
unlock_user_struct(uctx, unew_ctx, 1);
|
|
|
|
|
|
|
|
if (err) {
|
|
|
|
/* We cannot return to a partially updated context. */
|
|
|
|
force_sig(TARGET_SIGSEGV);
|
|
|
|
}
|
|
|
|
return -TARGET_QEMU_ESIGRETURN;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2021-09-29 15:05:46 +02:00
|
|
|
|
|
|
|
void setup_sigtramp(abi_ulong sigtramp_page)
|
|
|
|
{
|
|
|
|
uint32_t *tramp = lock_user(VERIFY_WRITE, sigtramp_page, 2 * 8, 0);
|
|
|
|
assert(tramp != NULL);
|
|
|
|
|
|
|
|
#ifdef TARGET_ARCH_HAS_SETUP_FRAME
|
|
|
|
default_sigreturn = sigtramp_page;
|
|
|
|
encode_trampoline(TARGET_NR_sigreturn, tramp + 0);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
default_rt_sigreturn = sigtramp_page + 8;
|
|
|
|
encode_trampoline(TARGET_NR_rt_sigreturn, tramp + 2);
|
|
|
|
|
|
|
|
unlock_user(tramp, sigtramp_page, 2 * 8);
|
|
|
|
}
|