2006-05-13 18:11:23 +02:00
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/*
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* QEMU PREP PCI host
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*
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* Copyright (c) 2006 Fabrice Bellard
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2012-05-26 19:14:52 +02:00
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* Copyright (c) 2011-2013 Andreas Färber
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2007-09-16 23:08:06 +02:00
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*
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2006-05-13 18:11:23 +02:00
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2013-02-04 15:40:22 +01:00
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#include "hw/hw.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/pci/pci_host.h"
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2013-02-05 17:06:20 +01:00
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#include "hw/i386/pc.h"
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2012-12-17 18:19:49 +01:00
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#include "exec/address-spaces.h"
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2006-05-13 18:11:23 +02:00
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2012-05-26 19:14:52 +02:00
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#define TYPE_RAVEN_PCI_DEVICE "raven"
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2012-08-20 19:08:04 +02:00
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#define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost"
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2012-05-26 19:14:52 +02:00
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#define RAVEN_PCI_DEVICE(obj) \
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OBJECT_CHECK(RavenPCIState, (obj), TYPE_RAVEN_PCI_DEVICE)
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typedef struct RavenPCIState {
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PCIDevice dev;
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} RavenPCIState;
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2012-08-20 19:08:04 +02:00
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#define RAVEN_PCI_HOST_BRIDGE(obj) \
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OBJECT_CHECK(PREPPCIState, (obj), TYPE_RAVEN_PCI_HOST_BRIDGE)
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2012-01-03 02:42:46 +01:00
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typedef struct PRePPCIState {
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2012-08-20 19:08:09 +02:00
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PCIHostState parent_obj;
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2012-08-20 19:08:04 +02:00
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2012-04-14 22:48:37 +02:00
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MemoryRegion intack;
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2012-01-03 02:42:46 +01:00
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qemu_irq irq[4];
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2012-05-26 19:14:52 +02:00
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PCIBus pci_bus;
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RavenPCIState pci_dev;
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2012-01-03 02:42:46 +01:00
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} PREPPCIState;
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2006-05-13 18:11:23 +02:00
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2012-10-23 12:30:10 +02:00
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static inline uint32_t PPC_PCIIO_config(hwaddr addr)
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2006-05-13 18:11:23 +02:00
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{
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int i;
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2012-08-20 19:08:04 +02:00
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for (i = 0; i < 11; i++) {
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if ((addr & (1 << (11 + i))) != 0) {
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2006-05-13 18:11:23 +02:00
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break;
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2012-08-20 19:08:04 +02:00
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}
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2006-05-13 18:11:23 +02:00
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}
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return (addr & 0x7ff) | (i << 11);
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}
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2012-10-23 12:30:10 +02:00
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static void ppc_pci_io_write(void *opaque, hwaddr addr,
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2012-01-07 08:28:53 +01:00
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uint64_t val, unsigned int size)
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2006-05-13 18:11:23 +02:00
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{
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PREPPCIState *s = opaque;
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2012-08-20 19:08:09 +02:00
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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pci_data_write(phb->bus, PPC_PCIIO_config(addr), val, size);
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2006-05-13 18:11:23 +02:00
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}
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2012-10-23 12:30:10 +02:00
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static uint64_t ppc_pci_io_read(void *opaque, hwaddr addr,
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2012-01-07 08:28:53 +01:00
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unsigned int size)
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2006-05-13 18:11:23 +02:00
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{
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PREPPCIState *s = opaque;
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2012-08-20 19:08:09 +02:00
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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return pci_data_read(phb->bus, PPC_PCIIO_config(addr), size);
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2006-05-13 18:11:23 +02:00
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}
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2011-11-21 16:16:57 +01:00
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static const MemoryRegionOps PPC_PCIIO_ops = {
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2012-01-07 08:28:53 +01:00
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.read = ppc_pci_io_read,
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.write = ppc_pci_io_write,
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2012-01-12 03:44:42 +01:00
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.endianness = DEVICE_LITTLE_ENDIAN,
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2006-05-13 18:11:23 +02:00
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};
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2012-10-23 12:30:10 +02:00
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static uint64_t ppc_intack_read(void *opaque, hwaddr addr,
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2012-04-14 22:48:37 +02:00
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unsigned int size)
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{
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return pic_read_irq(isa_pic);
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}
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static const MemoryRegionOps PPC_intack_ops = {
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.read = ppc_intack_read,
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.valid = {
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.max_access_size = 1,
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},
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};
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2006-09-24 02:16:34 +02:00
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static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
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2006-05-13 18:11:23 +02:00
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{
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2006-09-24 19:01:44 +02:00
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return (irq_num + (pci_dev->devfn >> 3)) & 1;
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2006-09-24 02:16:34 +02:00
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}
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2009-08-28 15:28:17 +02:00
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static void prep_set_irq(void *opaque, int irq_num, int level)
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2006-09-24 02:16:34 +02:00
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{
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2009-08-28 15:28:17 +02:00
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qemu_irq *pic = opaque;
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2012-01-03 02:42:46 +01:00
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qemu_set_irq(pic[irq_num] , level);
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2006-05-13 18:11:23 +02:00
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}
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2013-01-16 15:45:34 +01:00
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static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
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2006-05-13 18:11:23 +02:00
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{
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2013-01-16 15:45:34 +01:00
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SysBusDevice *dev = SYS_BUS_DEVICE(d);
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2012-08-20 19:08:08 +02:00
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PCIHostState *h = PCI_HOST_BRIDGE(dev);
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2012-08-20 19:08:04 +02:00
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PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev);
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2012-01-03 02:42:46 +01:00
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MemoryRegion *address_space_mem = get_system_memory();
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int i;
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2013-07-23 23:16:45 +02:00
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isa_mem_base = 0xc0000000;
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2012-01-03 02:42:46 +01:00
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for (i = 0; i < 4; i++) {
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sysbus_init_irq(dev, &s->irq[i]);
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}
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2006-05-13 18:11:23 +02:00
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2012-05-26 19:14:52 +02:00
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pci_bus_irqs(&s->pci_bus, prep_set_irq, prep_map_irq, s->irq, 4);
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2006-05-13 18:11:23 +02:00
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2013-06-07 03:25:08 +02:00
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memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, s,
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2011-07-24 16:47:18 +02:00
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"pci-conf-idx", 1);
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2012-01-03 02:42:46 +01:00
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sysbus_add_io(dev, 0xcf8, &h->conf_mem);
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sysbus_init_ioports(&h->busdev, 0xcf8, 1);
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2011-07-24 16:47:18 +02:00
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2013-06-07 03:25:08 +02:00
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memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_be_ops, s,
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2011-07-24 16:47:18 +02:00
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"pci-conf-data", 1);
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2012-01-03 02:42:46 +01:00
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sysbus_add_io(dev, 0xcfc, &h->data_mem);
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sysbus_init_ioports(&h->busdev, 0xcfc, 1);
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2006-05-13 18:11:23 +02:00
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2013-06-07 03:25:08 +02:00
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memory_region_init_io(&h->mmcfg, OBJECT(s), &PPC_PCIIO_ops, s, "pciio", 0x00400000);
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2012-01-03 02:42:46 +01:00
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memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
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2006-05-13 18:11:23 +02:00
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2013-06-07 03:25:08 +02:00
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memory_region_init_io(&s->intack, OBJECT(s), &PPC_intack_ops, s, "pci-intack", 1);
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2012-04-14 22:48:37 +02:00
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memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->intack);
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2012-01-03 01:50:07 +01:00
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2012-05-26 19:14:52 +02:00
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/* TODO Remove once realize propagates to child devices. */
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2013-01-16 15:45:34 +01:00
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object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp);
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2012-05-26 19:14:52 +02:00
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}
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static void raven_pcihost_initfn(Object *obj)
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{
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PCIHostState *h = PCI_HOST_BRIDGE(obj);
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PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj);
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MemoryRegion *address_space_mem = get_system_memory();
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MemoryRegion *address_space_io = get_system_io();
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DeviceState *pci_dev;
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2013-08-23 20:23:55 +02:00
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pci_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
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2013-03-14 23:01:11 +01:00
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address_space_mem, address_space_io, 0, TYPE_PCI_BUS);
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2012-05-26 19:14:52 +02:00
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h->bus = &s->pci_bus;
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2013-08-23 19:37:12 +02:00
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object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE);
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2012-05-26 19:14:52 +02:00
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pci_dev = DEVICE(&s->pci_dev);
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qdev_set_parent_bus(pci_dev, BUS(&s->pci_bus));
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object_property_set_int(OBJECT(&s->pci_dev), PCI_DEVFN(0, 0), "addr",
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NULL);
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qdev_prop_set_bit(pci_dev, "multifunction", false);
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2012-01-03 01:50:07 +01:00
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}
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static int raven_init(PCIDevice *d)
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{
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2006-05-13 18:11:23 +02:00
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d->config[0x0C] = 0x08; // cache_line_size
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d->config[0x0D] = 0x10; // latency_timer
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d->config[0x34] = 0x00; // capabilities_pointer
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2012-01-03 01:50:07 +01:00
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return 0;
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2006-05-13 18:11:23 +02:00
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}
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2012-01-03 01:50:07 +01:00
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static const VMStateDescription vmstate_raven = {
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.name = "raven",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(dev, RavenPCIState),
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VMSTATE_END_OF_LIST()
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},
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};
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2011-12-04 19:22:06 +01:00
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static void raven_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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2011-12-08 04:34:16 +01:00
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DeviceClass *dc = DEVICE_CLASS(klass);
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2011-12-04 19:22:06 +01:00
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k->init = raven_init;
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k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
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k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN;
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k->revision = 0x00;
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k->class_id = PCI_CLASS_BRIDGE_HOST;
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2011-12-08 04:34:16 +01:00
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dc->desc = "PReP Host Bridge - Motorola Raven";
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dc->vmsd = &vmstate_raven;
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qdev: Replace no_user by cannot_instantiate_with_device_add_yet
In an ideal world, machines can be built by wiring devices together
with configuration, not code. Unfortunately, that's not the world we
live in right now. We still have quite a few devices that need to be
wired up by code. If you try to device_add such a device, it'll fail
in sometimes mysterious ways. If you're lucky, you get an
unmysterious immediate crash.
To protect users from such badness, DeviceClass member no_user used to
make device models unavailable with -device / device_add, but that
regressed in commit 18b6dad. The device model is still omitted from
help, but is available anyway.
Attempts to fix the regression have been rejected with the argument
that the purpose of no_user isn't clear, and it's prone to misuse.
This commit clarifies no_user's purpose. Anthony suggested to rename
it cannot_instantiate_with_device_add_yet_due_to_internal_bugs, which
I shorten somewhat to keep checkpatch happy. While there, make it
bool.
Every use of cannot_instantiate_with_device_add_yet gets a FIXME
comment asking for rationale. The next few commits will clean them
all up, either by providing a rationale, or by getting rid of the use.
With that done, the regression fix is hopefully acceptable.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-28 17:26:54 +01:00
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dc->cannot_instantiate_with_device_add_yet = true; /* FIXME explain why */
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2011-12-04 19:22:06 +01:00
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}
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2012-08-20 19:07:56 +02:00
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static const TypeInfo raven_info = {
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2012-05-26 19:14:52 +02:00
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.name = TYPE_RAVEN_PCI_DEVICE,
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2011-12-08 04:34:16 +01:00
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(RavenPCIState),
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2011-12-04 19:22:06 +01:00
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.class_init = raven_class_init,
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2012-01-03 01:50:07 +01:00
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};
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2012-01-24 20:12:29 +01:00
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static void raven_pcihost_class_init(ObjectClass *klass, void *data)
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{
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2011-12-08 04:34:16 +01:00
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DeviceClass *dc = DEVICE_CLASS(klass);
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2012-01-24 20:12:29 +01:00
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2013-07-29 16:17:45 +02:00
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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2013-01-16 15:45:34 +01:00
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dc->realize = raven_pcihost_realizefn;
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2011-12-08 04:34:16 +01:00
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dc->fw_name = "pci";
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2012-01-24 20:12:29 +01:00
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}
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2012-08-20 19:07:56 +02:00
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static const TypeInfo raven_pcihost_info = {
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2012-08-20 19:08:04 +02:00
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.name = TYPE_RAVEN_PCI_HOST_BRIDGE,
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2012-08-20 19:08:08 +02:00
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.parent = TYPE_PCI_HOST_BRIDGE,
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2011-12-08 04:34:16 +01:00
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.instance_size = sizeof(PREPPCIState),
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2012-05-26 19:14:52 +02:00
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.instance_init = raven_pcihost_initfn,
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2012-01-24 20:12:29 +01:00
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.class_init = raven_pcihost_class_init,
|
2012-01-03 02:42:46 +01:00
|
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};
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|
2012-02-09 15:20:55 +01:00
|
|
|
static void raven_register_types(void)
|
2012-01-03 01:50:07 +01:00
|
|
|
{
|
2011-12-08 04:34:16 +01:00
|
|
|
type_register_static(&raven_pcihost_info);
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type_register_static(&raven_info);
|
2012-01-03 01:50:07 +01:00
|
|
|
}
|
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|
2012-02-09 15:20:55 +01:00
|
|
|
type_init(raven_register_types)
|