2009-08-28 15:28:13 +02:00
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/*
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* QEMU PIIX4 PCI Bridge Emulation
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*
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* Copyright (c) 2006 Fabrice Bellard
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2018-01-06 16:37:20 +01:00
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* Copyright (c) 2018 Hervé Poussineau
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2009-08-28 15:28:13 +02:00
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2016-01-26 19:17:03 +01:00
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#include "qemu/osdep.h"
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2018-01-06 16:37:26 +01:00
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#include "qapi/error.h"
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2018-01-06 16:37:21 +01:00
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#include "hw/irq.h"
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2019-02-02 01:13:12 +01:00
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#include "hw/southbridge/piix.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/pci/pci.h"
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2013-02-05 17:06:20 +01:00
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#include "hw/isa/isa.h"
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2019-12-12 17:15:43 +01:00
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#include "hw/intc/i8259.h"
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2018-01-06 16:37:22 +01:00
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#include "hw/dma/i8257.h"
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2018-01-06 16:37:23 +01:00
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#include "hw/timer/i8254.h"
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2018-01-06 16:37:26 +01:00
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#include "hw/rtc/mc146818rtc.h"
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2020-03-17 16:05:37 +01:00
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#include "hw/ide/pci.h"
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2019-08-12 07:23:45 +02:00
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#include "migration/vmstate.h"
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2018-01-06 16:37:20 +01:00
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#include "sysemu/reset.h"
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#include "sysemu/runstate.h"
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2020-09-03 22:43:22 +02:00
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#include "qom/object.h"
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2009-08-28 15:28:13 +02:00
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PCIDevice *piix4_dev;
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2020-09-03 22:43:22 +02:00
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struct PIIX4State {
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2010-12-02 16:26:56 +01:00
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PCIDevice dev;
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2018-01-06 16:37:21 +01:00
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qemu_irq cpu_intr;
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qemu_irq *isa;
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2018-01-06 16:37:20 +01:00
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2018-01-06 16:37:26 +01:00
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RTCState rtc;
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2018-01-06 16:37:20 +01:00
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/* Reset Control Register */
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MemoryRegion rcr_mem;
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uint8_t rcr;
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2020-09-03 22:43:22 +02:00
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};
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2010-12-02 16:26:56 +01:00
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2020-09-16 20:25:19 +02:00
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OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE)
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2015-05-13 02:43:24 +02:00
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2019-10-10 15:15:21 +02:00
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static void piix4_isa_reset(DeviceState *dev)
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2009-08-28 15:28:13 +02:00
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{
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2019-10-10 15:15:21 +02:00
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PIIX4State *d = PIIX4_PCI_DEVICE(dev);
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2010-12-02 16:26:56 +01:00
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uint8_t *pci_conf = d->dev.config;
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2009-08-28 15:28:13 +02:00
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pci_conf[0x04] = 0x07; // master, memory and I/O
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pci_conf[0x05] = 0x00;
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pci_conf[0x06] = 0x00;
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pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
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pci_conf[0x4c] = 0x4d;
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pci_conf[0x4e] = 0x03;
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pci_conf[0x4f] = 0x00;
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pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
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pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
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pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
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pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
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pci_conf[0x69] = 0x02;
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pci_conf[0x70] = 0x80;
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pci_conf[0x76] = 0x0c;
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pci_conf[0x77] = 0x0c;
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pci_conf[0x78] = 0x02;
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pci_conf[0x79] = 0x00;
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pci_conf[0x80] = 0x00;
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pci_conf[0x82] = 0x00;
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pci_conf[0xa0] = 0x08;
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pci_conf[0xa2] = 0x00;
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pci_conf[0xa3] = 0x00;
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pci_conf[0xa4] = 0x00;
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pci_conf[0xa5] = 0x00;
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pci_conf[0xa6] = 0x00;
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pci_conf[0xa7] = 0x00;
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pci_conf[0xa8] = 0x0f;
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pci_conf[0xaa] = 0x00;
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pci_conf[0xab] = 0x00;
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pci_conf[0xac] = 0x00;
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pci_conf[0xae] = 0x00;
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}
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2021-03-24 14:54:43 +01:00
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static int piix4_ide_post_load(void *opaque, int version_id)
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{
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PIIX4State *s = opaque;
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if (version_id == 2) {
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s->rcr = 0;
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}
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return 0;
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}
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2010-12-02 16:59:33 +01:00
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static const VMStateDescription vmstate_piix4 = {
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.name = "PIIX4",
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2021-03-24 14:54:43 +01:00
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.version_id = 3,
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2010-12-02 16:59:33 +01:00
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.minimum_version_id = 2,
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2021-03-24 14:54:43 +01:00
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.post_load = piix4_ide_post_load,
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2014-04-16 15:32:32 +02:00
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.fields = (VMStateField[]) {
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2010-12-02 16:59:33 +01:00
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VMSTATE_PCI_DEVICE(dev, PIIX4State),
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2021-03-24 14:54:43 +01:00
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VMSTATE_UINT8_V(rcr, PIIX4State, 3),
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2010-12-02 16:59:33 +01:00
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VMSTATE_END_OF_LIST()
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}
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};
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2009-08-28 15:28:13 +02:00
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2018-01-06 16:37:21 +01:00
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static void piix4_request_i8259_irq(void *opaque, int irq, int level)
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{
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PIIX4State *s = opaque;
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qemu_set_irq(s->cpu_intr, level);
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}
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static void piix4_set_i8259_irq(void *opaque, int irq, int level)
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{
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PIIX4State *s = opaque;
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qemu_set_irq(s->isa[irq], level);
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}
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2018-01-06 16:37:20 +01:00
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static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned int len)
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{
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PIIX4State *s = opaque;
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if (val & 4) {
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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return;
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}
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s->rcr = val & 2; /* keep System Reset type only */
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}
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static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len)
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{
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PIIX4State *s = opaque;
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return s->rcr;
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}
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static const MemoryRegionOps piix4_rcr_ops = {
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.read = piix4_rcr_read,
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.write = piix4_rcr_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 1,
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.max_access_size = 1,
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},
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};
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2015-01-19 15:52:30 +01:00
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static void piix4_realize(PCIDevice *dev, Error **errp)
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2009-08-28 15:28:13 +02:00
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{
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2018-01-06 16:37:20 +01:00
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PIIX4State *s = PIIX4_PCI_DEVICE(dev);
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2018-01-06 16:37:21 +01:00
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ISABus *isa_bus;
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qemu_irq *i8259_out_irq;
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2009-08-28 15:28:13 +02:00
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2018-01-06 16:37:21 +01:00
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isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
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pci_address_space_io(dev), errp);
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if (!isa_bus) {
|
isa: Clean up error handling around isa_bus_new()
We can have at most one ISA bus. If you try to create another one,
isa_bus_new() complains to stderr and returns null.
isa_bus_new() is called in two contexts, machine's init() and device's
realize() methods. Since complaining to stderr is not proper in the
latter context, convert isa_bus_new() to Error.
Machine's init():
* mips_jazz_init(), called from the init() methods of machines
"magnum" and "pica"
* mips_r4k_init(), the init() method of machine "mips"
* pc_init1() called from the init() methods of non-q35 PC machines
* typhoon_init(), called from clipper_init(), the init() method of
machine "clipper"
These callers always create the first ISA bus, hence isa_bus_new()
can't fail. Simply pass &error_abort.
Device's realize():
* i82378_realize(), of PCI device "i82378"
* ich9_lpc_realize(), of PCI device "ICH9-LPC"
* pci_ebus_realize(), of PCI device "ebus"
* piix3_realize(), of PCI device "pci-piix3", abstract parent of
"PIIX3" and "PIIX3-xen"
* piix4_realize(), of PCI device "PIIX4"
* vt82c686b_realize(), of PCI device "VT82C686B"
Propagate the error. Note that these devices are typically created
only by machine init() methods with qdev_init_nofail() or similar. If
we screwed up and created an ISA bus before that call, we now give up
right away. Before, we'd hobble on, and typically die in
isa_bus_irqs(). Similar if someone finds a way to hot-plug one of
these critters.
Cc: Richard Henderson <rth@twiddle.net>
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: "Hervé Poussineau" <hpoussin@reactos.org>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Markus Armbruster <armbru@pond.sub.org>
Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <1450370121-5768-11-git-send-email-armbru@redhat.com>
2015-12-17 17:35:18 +01:00
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return;
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}
|
2018-01-06 16:37:20 +01:00
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2018-01-06 16:37:21 +01:00
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qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
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"isa", ISA_NUM_IRQS);
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qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
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"intr", 1);
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2018-01-06 16:37:20 +01:00
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memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
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"reset-control", 1);
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memory_region_add_subregion_overlap(pci_address_space_io(dev),
|
2019-02-02 20:48:46 +01:00
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PIIX_RCR_IOPORT, &s->rcr_mem, 1);
|
2018-01-06 16:37:20 +01:00
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2018-01-06 16:37:21 +01:00
|
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/* initialize i8259 pic */
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i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
|
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s->isa = i8259_init(isa_bus, *i8259_out_irq);
|
2009-08-28 15:28:13 +02:00
|
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|
2018-01-06 16:37:21 +01:00
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/* initialize ISA irqs */
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isa_bus_irqs(isa_bus, s->isa);
|
2009-08-28 15:28:13 +02:00
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2018-01-06 16:37:23 +01:00
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/* initialize pit */
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i8254_pit_init(isa_bus, 0x40, 0, NULL);
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2018-01-06 16:37:22 +01:00
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/* DMA */
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i8257_dma_init(isa_bus, 0);
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2018-01-06 16:37:26 +01:00
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/* RTC */
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qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
|
error: Eliminate error_propagate() with Coccinelle, part 1
When all we do with an Error we receive into a local variable is
propagating to somewhere else, we can just as well receive it there
right away. Convert
if (!foo(..., &err)) {
...
error_propagate(errp, err);
...
return ...
}
to
if (!foo(..., errp)) {
...
...
return ...
}
where nothing else needs @err. Coccinelle script:
@rule1 forall@
identifier fun, err, errp, lbl;
expression list args, args2;
binary operator op;
constant c1, c2;
symbol false;
@@
if (
(
- fun(args, &err, args2)
+ fun(args, errp, args2)
|
- !fun(args, &err, args2)
+ !fun(args, errp, args2)
|
- fun(args, &err, args2) op c1
+ fun(args, errp, args2) op c1
)
)
{
... when != err
when != lbl:
when strict
- error_propagate(errp, err);
... when != err
(
return;
|
return c2;
|
return false;
)
}
@rule2 forall@
identifier fun, err, errp, lbl;
expression list args, args2;
expression var;
binary operator op;
constant c1, c2;
symbol false;
@@
- var = fun(args, &err, args2);
+ var = fun(args, errp, args2);
... when != err
if (
(
var
|
!var
|
var op c1
)
)
{
... when != err
when != lbl:
when strict
- error_propagate(errp, err);
... when != err
(
return;
|
return c2;
|
return false;
|
return var;
)
}
@depends on rule1 || rule2@
identifier err;
@@
- Error *err = NULL;
... when != err
Not exactly elegant, I'm afraid.
The "when != lbl:" is necessary to avoid transforming
if (fun(args, &err)) {
goto out
}
...
out:
error_propagate(errp, err);
even though other paths to label out still need the error_propagate().
For an actual example, see sclp_realize().
Without the "when strict", Coccinelle transforms vfio_msix_setup(),
incorrectly. I don't know what exactly "when strict" does, only that
it helps here.
The match of return is narrower than what I want, but I can't figure
out how to express "return where the operand doesn't use @err". For
an example where it's too narrow, see vfio_intx_enable().
Silently fails to convert hw/arm/armsse.c, because Coccinelle gets
confused by ARMSSE being used both as typedef and function-like macro
there. Converted manually.
Line breaks tidied up manually. One nested declaration of @local_err
deleted manually. Preexisting unwanted blank line dropped in
hw/riscv/sifive_e.c.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <20200707160613.848843-35-armbru@redhat.com>
2020-07-07 18:06:02 +02:00
|
|
|
if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) {
|
2018-01-06 16:37:26 +01:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, RTC_ISA_IRQ);
|
|
|
|
|
2018-01-06 16:37:21 +01:00
|
|
|
piix4_dev = dev;
|
2009-08-28 15:28:13 +02:00
|
|
|
}
|
|
|
|
|
2018-01-06 16:37:26 +01:00
|
|
|
static void piix4_init(Object *obj)
|
|
|
|
{
|
|
|
|
PIIX4State *s = PIIX4_PCI_DEVICE(obj);
|
|
|
|
|
|
|
|
object_initialize(&s->rtc, sizeof(s->rtc), TYPE_MC146818_RTC);
|
|
|
|
}
|
|
|
|
|
2011-12-04 19:22:06 +01:00
|
|
|
static void piix4_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 04:34:16 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2011-12-04 19:22:06 +01:00
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
|
2015-01-19 15:52:30 +01:00
|
|
|
k->realize = piix4_realize;
|
2011-12-04 19:22:06 +01:00
|
|
|
k->vendor_id = PCI_VENDOR_ID_INTEL;
|
|
|
|
k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
|
|
|
|
k->class_id = PCI_CLASS_BRIDGE_ISA;
|
2019-10-10 15:15:21 +02:00
|
|
|
dc->reset = piix4_isa_reset;
|
2011-12-08 04:34:16 +01:00
|
|
|
dc->desc = "ISA bridge";
|
|
|
|
dc->vmsd = &vmstate_piix4;
|
2013-11-28 17:27:00 +01:00
|
|
|
/*
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* Reason: part of PIIX4 southbridge, needs to be wired up,
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* e.g. by mips_malta_init()
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*/
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2017-05-03 22:35:44 +02:00
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dc->user_creatable = false;
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2014-02-05 16:36:48 +01:00
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dc->hotpluggable = false;
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2011-12-04 19:22:06 +01:00
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}
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2013-01-10 16:19:07 +01:00
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static const TypeInfo piix4_info = {
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2015-05-13 02:43:24 +02:00
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.name = TYPE_PIIX4_PCI_DEVICE,
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2011-12-08 04:34:16 +01:00
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PIIX4State),
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2018-01-06 16:37:26 +01:00
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.instance_init = piix4_init,
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2011-12-08 04:34:16 +01:00
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.class_init = piix4_class_init,
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2017-09-27 21:56:34 +02:00
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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2009-08-28 15:28:13 +02:00
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};
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|
2012-02-09 15:20:55 +01:00
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|
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static void piix4_register_types(void)
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2009-08-28 15:28:13 +02:00
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{
|
2011-12-08 04:34:16 +01:00
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type_register_static(&piix4_info);
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2009-08-28 15:28:13 +02:00
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}
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2012-02-09 15:20:55 +01:00
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type_init(piix4_register_types)
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2019-02-02 01:13:12 +01:00
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2020-03-17 16:05:37 +01:00
|
|
|
DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
|
2019-02-02 01:13:12 +01:00
|
|
|
{
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|
|
|
PCIDevice *pci;
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DeviceState *dev;
|
2020-03-17 16:05:37 +01:00
|
|
|
int devfn = PCI_DEVFN(10, 0);
|
2019-02-02 01:13:12 +01:00
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|
2020-03-17 16:05:37 +01:00
|
|
|
pci = pci_create_simple_multifunction(pci_bus, devfn, true,
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|
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TYPE_PIIX4_PCI_DEVICE);
|
2019-02-02 01:13:12 +01:00
|
|
|
dev = DEVICE(pci);
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|
|
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if (isa_bus) {
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|
*isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
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|
|
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}
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|
2020-03-17 16:05:37 +01:00
|
|
|
pci = pci_create_simple(pci_bus, devfn + 1, "piix4-ide");
|
2020-03-17 16:05:37 +01:00
|
|
|
pci_ide_create_devs(pci);
|
2020-03-17 16:05:37 +01:00
|
|
|
|
|
|
|
pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci");
|
2019-02-02 01:13:12 +01:00
|
|
|
if (smbus) {
|
2020-03-17 16:05:37 +01:00
|
|
|
*smbus = piix4_pm_init(pci_bus, devfn + 3, 0x1100,
|
2019-02-02 01:13:12 +01:00
|
|
|
isa_get_irq(NULL, 9), NULL, 0, NULL);
|
|
|
|
}
|
|
|
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|
|
return dev;
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|
|
|
}
|