2016-03-16 18:06:01 +01:00
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/*
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* OpenPOWER Palmetto BMC
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*
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* Andrew Jeffery <andrew@aj.id.au>
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*
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* Copyright 2016 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 09:01:28 +01:00
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#include "qapi/error.h"
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2019-05-23 15:47:43 +02:00
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#include "hw/arm/boot.h"
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2018-09-25 15:02:33 +02:00
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#include "hw/arm/aspeed.h"
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2016-09-22 19:13:05 +02:00
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#include "hw/arm/aspeed_soc.h"
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2021-06-08 22:25:22 +02:00
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#include "hw/i2c/i2c_mux_pca954x.h"
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2018-11-14 01:31:27 +01:00
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#include "hw/i2c/smbus_eeprom.h"
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2019-04-12 18:54:05 +02:00
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#include "hw/misc/pca9552.h"
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2021-05-18 23:08:03 +02:00
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#include "hw/sensor/tmp105.h"
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2020-06-20 18:54:41 +02:00
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#include "hw/misc/led.h"
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2019-08-12 07:23:51 +02:00
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#include "hw/qdev-properties.h"
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2016-07-04 14:06:38 +02:00
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#include "sysemu/block-backend.h"
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2017-01-20 12:15:08 +01:00
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#include "hw/loader.h"
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#include "qemu/error-report.h"
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2019-05-07 13:55:02 +02:00
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#include "qemu/units.h"
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2016-03-16 18:06:01 +01:00
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2016-09-22 19:13:05 +02:00
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static struct arm_boot_info aspeed_board_binfo = {
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2016-09-22 19:13:05 +02:00
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.board_id = -1, /* device-tree-only board */
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2016-03-16 18:06:01 +01:00
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};
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2020-06-23 09:21:31 +02:00
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struct AspeedMachineState {
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2020-06-23 09:21:32 +02:00
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/* Private */
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MachineState parent_obj;
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/* Public */
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2016-09-22 19:13:05 +02:00
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AspeedSoCState soc;
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2019-07-01 18:26:17 +02:00
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MemoryRegion ram_container;
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2018-08-16 15:05:29 +02:00
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MemoryRegion max_ram;
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2020-06-23 09:21:32 +02:00
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bool mmio_exec;
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2020-09-18 09:04:36 +02:00
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char *fmc_model;
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char *spi_model;
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2018-11-28 10:35:36 +01:00
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};
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2016-03-16 18:06:01 +01:00
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2016-12-27 15:59:27 +01:00
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/* Palmetto hardware value: 0x120CE416 */
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2016-09-22 19:13:05 +02:00
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#define PALMETTO_BMC_HW_STRAP1 ( \
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SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
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SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
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SCU_AST2400_HW_STRAP_ACPI_DIS | \
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SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
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SCU_HW_STRAP_VGA_CLASS_CODE | \
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SCU_HW_STRAP_LPC_RESET_PIN | \
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SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
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SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
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SCU_HW_STRAP_SPI_WIDTH | \
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SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
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SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
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2020-09-01 14:21:50 +02:00
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/* TODO: Find the actual hardware value */
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#define SUPERMICROX11_BMC_HW_STRAP1 ( \
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SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
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SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \
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SCU_AST2400_HW_STRAP_ACPI_DIS | \
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SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
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SCU_HW_STRAP_VGA_CLASS_CODE | \
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SCU_HW_STRAP_LPC_RESET_PIN | \
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SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
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SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
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SCU_HW_STRAP_SPI_WIDTH | \
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SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
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SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
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2016-12-27 15:59:27 +01:00
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/* AST2500 evb hardware value: 0xF100C2E6 */
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2016-09-22 19:13:06 +02:00
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#define AST2500_EVB_HW_STRAP1 (( \
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AST2500_HW_STRAP1_DEFAULTS | \
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SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
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SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
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SCU_AST2500_HW_STRAP_UART_DEBUG | \
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SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
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SCU_HW_STRAP_MAC1_RGMII | \
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SCU_HW_STRAP_MAC0_RGMII) & \
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~SCU_HW_STRAP_2ND_BOOT_WDT)
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2016-12-27 15:59:27 +01:00
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/* Romulus hardware value: 0xF10AD206 */
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#define ROMULUS_BMC_HW_STRAP1 ( \
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AST2500_HW_STRAP1_DEFAULTS | \
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SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
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SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
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SCU_AST2500_HW_STRAP_UART_DEBUG | \
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SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
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SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
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SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
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2020-05-06 20:32:19 +02:00
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/* Sonorapass hardware value: 0xF100D216 */
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#define SONORAPASS_BMC_HW_STRAP1 ( \
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SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
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SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
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SCU_AST2500_HW_STRAP_UART_DEBUG | \
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SCU_AST2500_HW_STRAP_RESERVED28 | \
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SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
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SCU_HW_STRAP_VGA_CLASS_CODE | \
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SCU_HW_STRAP_LPC_RESET_PIN | \
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SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
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SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
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SCU_HW_STRAP_VGA_BIOS_ROM | \
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SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
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SCU_AST2500_HW_STRAP_RESERVED1)
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2019-07-01 18:26:17 +02:00
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/* Swift hardware value: 0xF11AD206 */
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#define SWIFT_BMC_HW_STRAP1 ( \
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AST2500_HW_STRAP1_DEFAULTS | \
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SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
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SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
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SCU_AST2500_HW_STRAP_UART_DEBUG | \
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SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
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SCU_H_PLL_BYPASS_EN | \
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SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
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SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
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2020-12-10 12:11:03 +01:00
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#define G220A_BMC_HW_STRAP1 ( \
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SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
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SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
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SCU_AST2500_HW_STRAP_UART_DEBUG | \
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SCU_AST2500_HW_STRAP_RESERVED28 | \
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SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
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SCU_HW_STRAP_2ND_BOOT_WDT | \
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SCU_HW_STRAP_VGA_CLASS_CODE | \
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SCU_HW_STRAP_LPC_RESET_PIN | \
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SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
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SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
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SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \
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SCU_AST2500_HW_STRAP_RESERVED1)
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2018-06-08 14:15:32 +02:00
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/* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
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#define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
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2021-05-01 10:03:52 +02:00
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/* Quanta-Q71l hardware value */
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#define QUANTA_Q71L_BMC_HW_STRAP1 ( \
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SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
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SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
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SCU_AST2400_HW_STRAP_ACPI_DIS | \
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SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \
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SCU_HW_STRAP_VGA_CLASS_CODE | \
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SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \
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SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
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SCU_HW_STRAP_SPI_WIDTH | \
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SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \
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SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
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2019-10-23 15:04:55 +02:00
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/* AST2600 evb hardware value */
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#define AST2600_EVB_HW_STRAP1 0x000000C0
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#define AST2600_EVB_HW_STRAP2 0x00000003
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2019-11-19 15:12:08 +01:00
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/* Tacoma hardware value */
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#define TACOMA_BMC_HW_STRAP1 0x00000000
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2020-05-04 11:37:03 +02:00
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#define TACOMA_BMC_HW_STRAP2 0x00000040
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2019-11-19 15:12:08 +01:00
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2021-05-01 10:03:52 +02:00
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/* Rainier hardware value: (QEMU prototype) */
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#define RAINIER_BMC_HW_STRAP1 0x00000000
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#define RAINIER_BMC_HW_STRAP2 0x00000000
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2018-08-16 15:05:29 +02:00
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/*
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* The max ram region is for firmwares that scan the address space
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* with load/store to guess how much RAM the SoC has.
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*/
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static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size)
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{
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return 0;
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}
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static void max_ram_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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/* Discard writes */
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}
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static const MemoryRegionOps max_ram_ops = {
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.read = max_ram_read,
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.write = max_ram_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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2020-04-09 08:31:37 +02:00
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#define AST_SMP_MAILBOX_BASE 0x1e6e2180
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#define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
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#define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
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#define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
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#define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
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#define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
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#define AST_SMP_MBOX_GOSIGN 0xabbaab00
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static void aspeed_write_smpboot(ARMCPU *cpu,
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const struct arm_boot_info *info)
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{
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static const uint32_t poll_mailbox_ready[] = {
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/*
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* r2 = per-cpu go sign value
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* r1 = AST_SMP_MBOX_FIELD_ENTRY
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* r0 = AST_SMP_MBOX_FIELD_GOSIGN
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*/
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0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
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0xe21000ff, /* ands r0, r0, #255 */
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0xe59f201c, /* ldr r2, [pc, #28] */
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0xe1822000, /* orr r2, r2, r0 */
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0xe59f1018, /* ldr r1, [pc, #24] */
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0xe59f0018, /* ldr r0, [pc, #24] */
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0xe320f002, /* wfe */
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0xe5904000, /* ldr r4, [r0] */
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0xe1520004, /* cmp r2, r4 */
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0x1afffffb, /* bne <wfe> */
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0xe591f000, /* ldr pc, [r1] */
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AST_SMP_MBOX_GOSIGN,
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AST_SMP_MBOX_FIELD_ENTRY,
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AST_SMP_MBOX_FIELD_GOSIGN,
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};
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rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
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sizeof(poll_mailbox_ready),
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info->smp_loader_start);
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}
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static void aspeed_reset_secondary(ARMCPU *cpu,
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const struct arm_boot_info *info)
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{
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AddressSpace *as = arm_boot_address_space(cpu, info);
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CPUState *cs = CPU(cpu);
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/* info->smp_bootreg_addr */
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address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
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MEMTXATTRS_UNSPECIFIED, NULL);
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cpu_set_pc(cs, info->smp_loader_start);
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}
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|
2017-01-20 12:15:08 +01:00
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#define FIRMWARE_ADDR 0x0
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static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
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Error **errp)
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{
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BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
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uint8_t *storage;
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2017-02-10 18:40:29 +01:00
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int64_t size;
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/* The block backend size should have already been 'validated' by
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* the creation of the m25p80 object.
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*/
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size = blk_getlength(blk);
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if (size <= 0) {
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error_setg(errp, "failed to get flash size");
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return;
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}
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2017-01-20 12:15:08 +01:00
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2017-02-10 18:40:29 +01:00
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if (rom_size > size) {
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rom_size = size;
|
2017-01-20 12:15:08 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
storage = g_new0(uint8_t, rom_size);
|
|
|
|
if (blk_pread(blk, 0, storage, rom_size) < 0) {
|
|
|
|
error_setg(errp, "failed to read the initial flash content");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
|
|
|
|
g_free(storage);
|
|
|
|
}
|
|
|
|
|
2020-06-22 11:42:25 +02:00
|
|
|
static void aspeed_board_init_flashes(AspeedSMCState *s,
|
|
|
|
const char *flashtype)
|
2016-07-04 14:06:38 +02:00
|
|
|
{
|
|
|
|
int i ;
|
|
|
|
|
|
|
|
for (i = 0; i < s->num_cs; ++i) {
|
|
|
|
AspeedSMCFlash *fl = &s->flashes[i];
|
|
|
|
DriveInfo *dinfo = drive_get_next(IF_MTD);
|
|
|
|
qemu_irq cs_line;
|
|
|
|
|
ssi: Convert uses of ssi_create_slave_no_init() with Coccinelle
Replace
dev = ssi_create_slave_no_init(bus, type_name);
...
qdev_init_nofail(dev);
by
dev = qdev_new(type_name);
...
qdev_realize_and_unref(dev, bus, &error_fatal);
Recent commit "qdev: New qdev_new(), qdev_realize(), etc." explains
why.
@@
type SSIBus;
identifier bus;
expression dev, qbus, expr;
expression list args;
@@
- bus = (SSIBus *)qbus;
+ bus = qbus; // TODO fix up decl
...
- dev = ssi_create_slave_no_init(bus, args);
+ dev = qdev_new(args);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression dev, bus, expr;
expression list args;
@@
- dev = ssi_create_slave_no_init(bus, args);
+ dev = qdev_new(args);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, BUS(bus), &error_fatal);
Bus declarations fixed up manually.
Cc: Alistair Francis <alistair@alistair23.me>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-24-armbru@redhat.com>
2020-06-10 07:32:12 +02:00
|
|
|
fl->flash = qdev_new(flashtype);
|
2016-07-04 14:06:38 +02:00
|
|
|
if (dinfo) {
|
2020-06-22 11:42:25 +02:00
|
|
|
qdev_prop_set_drive(fl->flash, "drive",
|
|
|
|
blk_by_legacy_dinfo(dinfo));
|
2016-07-04 14:06:38 +02:00
|
|
|
}
|
ssi: Convert uses of ssi_create_slave_no_init() with Coccinelle
Replace
dev = ssi_create_slave_no_init(bus, type_name);
...
qdev_init_nofail(dev);
by
dev = qdev_new(type_name);
...
qdev_realize_and_unref(dev, bus, &error_fatal);
Recent commit "qdev: New qdev_new(), qdev_realize(), etc." explains
why.
@@
type SSIBus;
identifier bus;
expression dev, qbus, expr;
expression list args;
@@
- bus = (SSIBus *)qbus;
+ bus = qbus; // TODO fix up decl
...
- dev = ssi_create_slave_no_init(bus, args);
+ dev = qdev_new(args);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression dev, bus, expr;
expression list args;
@@
- dev = ssi_create_slave_no_init(bus, args);
+ dev = qdev_new(args);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, BUS(bus), &error_fatal);
Bus declarations fixed up manually.
Cc: Alistair Francis <alistair@alistair23.me>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-24-armbru@redhat.com>
2020-06-10 07:32:12 +02:00
|
|
|
qdev_realize_and_unref(fl->flash, BUS(s->spi), &error_fatal);
|
2016-07-04 14:06:38 +02:00
|
|
|
|
|
|
|
cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0);
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-01-30 17:02:02 +01:00
|
|
|
static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
|
|
|
|
{
|
|
|
|
DeviceState *card;
|
|
|
|
|
2020-07-13 15:36:12 +02:00
|
|
|
if (!dinfo) {
|
|
|
|
return;
|
2020-01-30 17:02:02 +01:00
|
|
|
}
|
2020-07-13 15:36:12 +02:00
|
|
|
card = qdev_new(TYPE_SD_CARD);
|
|
|
|
qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
|
|
|
|
&error_fatal);
|
qdev: Convert uses of qdev_create() with Coccinelle
This is the transformation explained in the commit before previous.
Takes care of just one pattern that needs conversion. More to come in
this series.
Coccinelle script:
@ depends on !(file in "hw/arm/highbank.c")@
expression bus, type_name, dev, expr;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr;
identifier DOWN;
@@
- dev = DOWN(qdev_create(bus, type_name));
+ dev = DOWN(qdev_new(type_name));
... when != dev = expr
- qdev_init_nofail(DEVICE(dev));
+ qdev_realize_and_unref(DEVICE(dev), bus, &error_fatal);
@@
expression bus, type_name, expr;
identifier dev;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr, errp;
symbol true;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
@@
expression bus, type_name, expr, errp;
identifier dev;
symbol true;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
The first rule exempts hw/arm/highbank.c, because it matches along two
control flow paths there, with different @type_name. Covered by the
next commit's manual conversions.
Missing #include "qapi/error.h" added manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-10-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 07:31:58 +02:00
|
|
|
qdev_realize_and_unref(card,
|
|
|
|
qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
|
|
|
|
&error_fatal);
|
2020-01-30 17:02:02 +01:00
|
|
|
}
|
|
|
|
|
2019-11-19 15:12:07 +01:00
|
|
|
static void aspeed_machine_init(MachineState *machine)
|
2016-03-16 18:06:01 +01:00
|
|
|
{
|
2020-06-23 09:21:32 +02:00
|
|
|
AspeedMachineState *bmc = ASPEED_MACHINE(machine);
|
2019-11-19 15:12:07 +01:00
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
|
2016-09-22 19:13:05 +02:00
|
|
|
AspeedSoCClass *sc;
|
2017-01-20 12:15:08 +01:00
|
|
|
DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
|
2018-08-16 15:05:29 +02:00
|
|
|
ram_addr_t max_ram_size;
|
2019-09-25 16:32:27 +02:00
|
|
|
int i;
|
arm/aspeed: Rework NIC attachment
The number of MACs supported by an Aspeed SoC is defined by "macs_num"
under the SoC model, that is two for the AST2400 and AST2500 and four
for the AST2600. The model initializes the maximum number of supported
MACs but the number of realized devices is capped by the number of
network device back-ends defined on the command line. This can leave
unrealized devices hanging around in the QOM composition tree.
To get virtual hardware that matches the physical hardware, you have
to pass exactly as many -nic options as there are MACs, and some of
them must be -nic none:
* Machines ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc,
swift-bmc, and witherspoon-bmc: two -nic, and the second one must be
-nic none.
* Machine ast2600-evb: four -nic, the first one must be -nic none.
* Machine tacoma-bmc: four nic, the first two and the last one must be
-nic none.
Modify the machine initialization to define which MACs are attached to
a network device back-end using a bit-field property "macs-mask" and
let the SoC realize all network devices.
The default setting of "macs-mask" is "use MAC0" only, which works for
all our AST2400 and AST2500 machines. The AST2600 machines have
different configurations. The AST2600 EVB machine activates MAC1, MAC2
and MAC3 and the Tacoma BMC machine activates MAC2.
Incompatible CLI change: -nic options now apply to *active* MACs:
MAC1, MAC2, MAC3 for ast2600-evb, MAC2 for tacoma-bmc, and MAC0 for
all the others.
The machines now always get all MACs as they should. Visible in "info
qom-tree", here's the change for tacoma-bmc:
/machine (tacoma-bmc-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
[...]
/ftgmac100[0] (ftgmac100)
/ftgmac100[0] (qemu:memory-region)
/ftgmac100[1] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
/ftgmac100[2] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
/ftgmac100[3] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
[...]
/mii[0] (aspeed-mmi)
/aspeed-mmi[0] (qemu:memory-region)
/mii[1] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
/mii[2] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
/mii[3] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
Also visible in "info qtree"; here's the change for tacoma-bmc:
dev: ftgmac100, id ""
gpio-out "sysbus-irq" 1
aspeed = true
- mac = "52:54:00:12:34:56"
- netdev = "hub0port0"
+ mac = "52:54:00:12:34:57"
+ netdev = ""
mmio 000000001e660000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:58"
netdev = ""
+ mmio 000000001e680000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
- netdev = ""
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:56"
+ netdev = "hub0port0"
+ mmio 000000001e670000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:59"
netdev = ""
+ mmio 000000001e690000/0000000000002000
[...]
dev: aspeed-mmi, id ""
mmio 000000001e650000/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650008/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650010/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650018/0000000000000008
Inactive MACs will have no peer and QEMU may warn the user with :
qemu-system-arm: warning: nic ftgmac100.0 has no peer
qemu-system-arm: warning: nic ftgmac100.1 has no peer
qemu-system-arm: warning: nic ftgmac100.3 has no peer
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-6-armbru@redhat.com>
2020-06-09 14:23:20 +02:00
|
|
|
NICInfo *nd = &nd_table[0];
|
2016-03-16 18:06:01 +01:00
|
|
|
|
2019-07-01 18:26:17 +02:00
|
|
|
memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container",
|
2020-06-01 16:29:23 +02:00
|
|
|
4 * GiB);
|
2020-02-19 17:08:44 +01:00
|
|
|
memory_region_add_subregion(&bmc->ram_container, 0, machine->ram);
|
2019-07-01 18:26:17 +02:00
|
|
|
|
qom: Less verbose object_initialize_child()
All users of object_initialize_child() pass the obvious child size
argument. Almost all pass &error_abort and no properties. Tiresome.
Rename object_initialize_child() to
object_initialize_child_with_props() to free the name. New
convenience wrapper object_initialize_child() automates the size
argument, and passes &error_abort and no properties.
Rename object_initialize_childv() to
object_initialize_child_with_propsv() for consistency.
Convert callers with this Coccinelle script:
@@
expression parent, propname, type;
expression child, size;
symbol error_abort;
@@
- object_initialize_child(parent, propname, OBJECT(child), size, type, &error_abort, NULL)
+ object_initialize_child(parent, propname, child, size, type, &error_abort, NULL)
@@
expression parent, propname, type;
expression child;
symbol error_abort;
@@
- object_initialize_child(parent, propname, child, sizeof(*child), type, &error_abort, NULL)
+ object_initialize_child(parent, propname, child, type)
@@
expression parent, propname, type;
expression child;
symbol error_abort;
@@
- object_initialize_child(parent, propname, &child, sizeof(child), type, &error_abort, NULL)
+ object_initialize_child(parent, propname, &child, type)
@@
expression parent, propname, type;
expression child, size, err;
expression list props;
@@
- object_initialize_child(parent, propname, child, size, type, err, props)
+ object_initialize_child_with_props(parent, propname, child, size, type, err, props)
Note that Coccinelle chokes on ARMSSE typedef vs. macro in
hw/arm/armsse.c. Worked around by temporarily renaming the macro for
the spatch run.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
[Rebased: machine opentitan is new (commit fe0fe4735e7)]
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-37-armbru@redhat.com>
2020-06-10 07:32:25 +02:00
|
|
|
object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
|
2016-03-16 18:06:01 +01:00
|
|
|
|
2016-09-22 19:13:05 +02:00
|
|
|
sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
|
|
|
|
|
2020-02-19 17:08:43 +01:00
|
|
|
/*
|
|
|
|
* This will error out if isize is not supported by memory controller.
|
|
|
|
*/
|
2020-10-28 11:18:20 +01:00
|
|
|
object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
|
2020-02-19 17:08:43 +01:00
|
|
|
&error_fatal);
|
|
|
|
|
arm/aspeed: Rework NIC attachment
The number of MACs supported by an Aspeed SoC is defined by "macs_num"
under the SoC model, that is two for the AST2400 and AST2500 and four
for the AST2600. The model initializes the maximum number of supported
MACs but the number of realized devices is capped by the number of
network device back-ends defined on the command line. This can leave
unrealized devices hanging around in the QOM composition tree.
To get virtual hardware that matches the physical hardware, you have
to pass exactly as many -nic options as there are MACs, and some of
them must be -nic none:
* Machines ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc,
swift-bmc, and witherspoon-bmc: two -nic, and the second one must be
-nic none.
* Machine ast2600-evb: four -nic, the first one must be -nic none.
* Machine tacoma-bmc: four nic, the first two and the last one must be
-nic none.
Modify the machine initialization to define which MACs are attached to
a network device back-end using a bit-field property "macs-mask" and
let the SoC realize all network devices.
The default setting of "macs-mask" is "use MAC0" only, which works for
all our AST2400 and AST2500 machines. The AST2600 machines have
different configurations. The AST2600 EVB machine activates MAC1, MAC2
and MAC3 and the Tacoma BMC machine activates MAC2.
Incompatible CLI change: -nic options now apply to *active* MACs:
MAC1, MAC2, MAC3 for ast2600-evb, MAC2 for tacoma-bmc, and MAC0 for
all the others.
The machines now always get all MACs as they should. Visible in "info
qom-tree", here's the change for tacoma-bmc:
/machine (tacoma-bmc-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
[...]
/ftgmac100[0] (ftgmac100)
/ftgmac100[0] (qemu:memory-region)
/ftgmac100[1] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
/ftgmac100[2] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
/ftgmac100[3] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
[...]
/mii[0] (aspeed-mmi)
/aspeed-mmi[0] (qemu:memory-region)
/mii[1] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
/mii[2] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
/mii[3] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
Also visible in "info qtree"; here's the change for tacoma-bmc:
dev: ftgmac100, id ""
gpio-out "sysbus-irq" 1
aspeed = true
- mac = "52:54:00:12:34:56"
- netdev = "hub0port0"
+ mac = "52:54:00:12:34:57"
+ netdev = ""
mmio 000000001e660000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:58"
netdev = ""
+ mmio 000000001e680000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
- netdev = ""
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:56"
+ netdev = "hub0port0"
+ mmio 000000001e670000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:59"
netdev = ""
+ mmio 000000001e690000/0000000000002000
[...]
dev: aspeed-mmi, id ""
mmio 000000001e650000/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650008/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650010/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650018/0000000000000008
Inactive MACs will have no peer and QEMU may warn the user with :
qemu-system-arm: warning: nic ftgmac100.0 has no peer
qemu-system-arm: warning: nic ftgmac100.1 has no peer
qemu-system-arm: warning: nic ftgmac100.3 has no peer
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-6-armbru@redhat.com>
2020-06-09 14:23:20 +02:00
|
|
|
for (i = 0; i < sc->macs_num; i++) {
|
|
|
|
if ((amc->macs_mask & (1 << i)) && nd->used) {
|
|
|
|
qemu_check_nic_model(nd, TYPE_FTGMAC100);
|
|
|
|
qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
|
|
|
|
nd++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
qom: Put name parameter before value / visitor parameter
The object_property_set_FOO() setters take property name and value in
an unusual order:
void object_property_set_FOO(Object *obj, FOO_TYPE value,
const char *name, Error **errp)
Having to pass value before name feels grating. Swap them.
Same for object_property_set(), object_property_get(), and
object_property_parse().
Convert callers with this Coccinelle script:
@@
identifier fun = {
object_property_get, object_property_parse, object_property_set_str,
object_property_set_link, object_property_set_bool,
object_property_set_int, object_property_set_uint, object_property_set,
object_property_set_qobject
};
expression obj, v, name, errp;
@@
- fun(obj, v, name, errp)
+ fun(obj, name, v, errp)
Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error
message "no position information". Convert that one manually.
Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by
ARMSSE being used both as typedef and function-like macro there.
Convert manually.
Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused
by RXCPU being used both as typedef and function-like macro there.
Convert manually. The other files using RXCPU that way don't need
conversion.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20200707160613.848843-27-armbru@redhat.com>
[Straightforwad conflict with commit 2336172d9b "audio: set default
value for pcspk.iobase property" resolved]
2020-07-07 18:05:54 +02:00
|
|
|
object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
|
2016-06-27 16:37:33 +02:00
|
|
|
&error_abort);
|
qom: Put name parameter before value / visitor parameter
The object_property_set_FOO() setters take property name and value in
an unusual order:
void object_property_set_FOO(Object *obj, FOO_TYPE value,
const char *name, Error **errp)
Having to pass value before name feels grating. Swap them.
Same for object_property_set(), object_property_get(), and
object_property_parse().
Convert callers with this Coccinelle script:
@@
identifier fun = {
object_property_get, object_property_parse, object_property_set_str,
object_property_set_link, object_property_set_bool,
object_property_set_int, object_property_set_uint, object_property_set,
object_property_set_qobject
};
expression obj, v, name, errp;
@@
- fun(obj, v, name, errp)
+ fun(obj, name, v, errp)
Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error
message "no position information". Convert that one manually.
Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by
ARMSSE being used both as typedef and function-like macro there.
Convert manually.
Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused
by RXCPU being used both as typedef and function-like macro there.
Convert manually. The other files using RXCPU that way don't need
conversion.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20200707160613.848843-27-armbru@redhat.com>
[Straightforwad conflict with commit 2336172d9b "audio: set default
value for pcspk.iobase property" resolved]
2020-07-07 18:05:54 +02:00
|
|
|
object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
|
2019-10-23 15:04:55 +02:00
|
|
|
&error_abort);
|
qom: Put name parameter before value / visitor parameter
The object_property_set_FOO() setters take property name and value in
an unusual order:
void object_property_set_FOO(Object *obj, FOO_TYPE value,
const char *name, Error **errp)
Having to pass value before name feels grating. Swap them.
Same for object_property_set(), object_property_get(), and
object_property_parse().
Convert callers with this Coccinelle script:
@@
identifier fun = {
object_property_get, object_property_parse, object_property_set_str,
object_property_set_link, object_property_set_bool,
object_property_set_int, object_property_set_uint, object_property_set,
object_property_set_qobject
};
expression obj, v, name, errp;
@@
- fun(obj, v, name, errp)
+ fun(obj, name, v, errp)
Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error
message "no position information". Convert that one manually.
Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by
ARMSSE being used both as typedef and function-like macro there.
Convert manually.
Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused
by RXCPU being used both as typedef and function-like macro there.
Convert manually. The other files using RXCPU that way don't need
conversion.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20200707160613.848843-27-armbru@redhat.com>
[Straightforwad conflict with commit 2336172d9b "audio: set default
value for pcspk.iobase property" resolved]
2020-07-07 18:05:54 +02:00
|
|
|
object_property_set_int(OBJECT(&bmc->soc), "num-cs", amc->num_cs,
|
2016-12-27 15:59:29 +01:00
|
|
|
&error_abort);
|
qom: Put name parameter before value / visitor parameter
The object_property_set_FOO() setters take property name and value in
an unusual order:
void object_property_set_FOO(Object *obj, FOO_TYPE value,
const char *name, Error **errp)
Having to pass value before name feels grating. Swap them.
Same for object_property_set(), object_property_get(), and
object_property_parse().
Convert callers with this Coccinelle script:
@@
identifier fun = {
object_property_get, object_property_parse, object_property_set_str,
object_property_set_link, object_property_set_bool,
object_property_set_int, object_property_set_uint, object_property_set,
object_property_set_qobject
};
expression obj, v, name, errp;
@@
- fun(obj, v, name, errp)
+ fun(obj, name, v, errp)
Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error
message "no position information". Convert that one manually.
Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by
ARMSSE being used both as typedef and function-like macro there.
Convert manually.
Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused
by RXCPU being used both as typedef and function-like macro there.
Convert manually. The other files using RXCPU that way don't need
conversion.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20200707160613.848843-27-armbru@redhat.com>
[Straightforwad conflict with commit 2336172d9b "audio: set default
value for pcspk.iobase property" resolved]
2020-07-07 18:05:54 +02:00
|
|
|
object_property_set_link(OBJECT(&bmc->soc), "dram",
|
2021-05-01 10:03:51 +02:00
|
|
|
OBJECT(machine->ram), &error_abort);
|
2017-11-14 13:20:18 +01:00
|
|
|
if (machine->kernel_filename) {
|
|
|
|
/*
|
|
|
|
* When booting with a -kernel command line there is no u-boot
|
|
|
|
* that runs to unlock the SCU. In this case set the default to
|
|
|
|
* be unlocked as the kernel expects
|
|
|
|
*/
|
qom: Put name parameter before value / visitor parameter
The object_property_set_FOO() setters take property name and value in
an unusual order:
void object_property_set_FOO(Object *obj, FOO_TYPE value,
const char *name, Error **errp)
Having to pass value before name feels grating. Swap them.
Same for object_property_set(), object_property_get(), and
object_property_parse().
Convert callers with this Coccinelle script:
@@
identifier fun = {
object_property_get, object_property_parse, object_property_set_str,
object_property_set_link, object_property_set_bool,
object_property_set_int, object_property_set_uint, object_property_set,
object_property_set_qobject
};
expression obj, v, name, errp;
@@
- fun(obj, v, name, errp)
+ fun(obj, name, v, errp)
Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error
message "no position information". Convert that one manually.
Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by
ARMSSE being used both as typedef and function-like macro there.
Convert manually.
Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused
by RXCPU being used both as typedef and function-like macro there.
Convert manually. The other files using RXCPU that way don't need
conversion.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20200707160613.848843-27-armbru@redhat.com>
[Straightforwad conflict with commit 2336172d9b "audio: set default
value for pcspk.iobase property" resolved]
2020-07-07 18:05:54 +02:00
|
|
|
object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
|
|
|
|
ASPEED_SCU_PROT_KEY, &error_abort);
|
2017-11-14 13:20:18 +01:00
|
|
|
}
|
qdev: Convert bus-less devices to qdev_realize() with Coccinelle
All remaining conversions to qdev_realize() are for bus-less devices.
Coccinelle script:
// only correct for bus-less @dev!
@@
expression errp;
expression dev;
@@
- qdev_init_nofail(dev);
+ qdev_realize(dev, NULL, &error_fatal);
@ depends on !(file in "hw/core/qdev.c") && !(file in "hw/core/bus.c")@
expression errp;
expression dev;
symbol true;
@@
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize(DEVICE(dev), NULL, errp);
@ depends on !(file in "hw/core/qdev.c") && !(file in "hw/core/bus.c")@
expression errp;
expression dev;
symbol true;
@@
- object_property_set_bool(dev, true, "realized", errp);
+ qdev_realize(DEVICE(dev), NULL, errp);
Note that Coccinelle chokes on ARMSSE typedef vs. macro in
hw/arm/armsse.c. Worked around by temporarily renaming the macro for
the spatch run.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-57-armbru@redhat.com>
2020-06-10 07:32:45 +02:00
|
|
|
qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
|
2016-03-16 18:06:01 +01:00
|
|
|
|
2019-07-01 18:26:15 +02:00
|
|
|
memory_region_add_subregion(get_system_memory(),
|
2020-08-25 21:20:02 +02:00
|
|
|
sc->memmap[ASPEED_DEV_SDRAM],
|
2019-07-01 18:26:17 +02:00
|
|
|
&bmc->ram_container);
|
2016-09-22 19:13:06 +02:00
|
|
|
|
2018-08-16 15:05:29 +02:00
|
|
|
max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
|
|
|
|
&error_abort);
|
|
|
|
memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
|
2020-10-28 11:18:20 +01:00
|
|
|
"max_ram", max_ram_size - machine->ram_size);
|
|
|
|
memory_region_add_subregion(&bmc->ram_container, machine->ram_size, &bmc->max_ram);
|
2018-08-16 15:05:29 +02:00
|
|
|
|
2020-09-18 09:04:36 +02:00
|
|
|
aspeed_board_init_flashes(&bmc->soc.fmc, bmc->fmc_model ?
|
|
|
|
bmc->fmc_model : amc->fmc_model);
|
|
|
|
aspeed_board_init_flashes(&bmc->soc.spi[0], bmc->spi_model ?
|
|
|
|
bmc->spi_model : amc->spi_model);
|
2016-09-22 19:13:05 +02:00
|
|
|
|
2017-01-20 12:15:08 +01:00
|
|
|
/* Install first FMC flash content as a boot rom. */
|
|
|
|
if (drive0) {
|
|
|
|
AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0];
|
|
|
|
MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* create a ROM region using the default mapping window size of
|
2017-02-10 18:40:29 +01:00
|
|
|
* the flash module. The window size is 64MB for the AST2400
|
|
|
|
* SoC and 128MB for the AST2500 SoC, which is twice as big as
|
|
|
|
* needed by the flash modules of the Aspeed machines.
|
2017-01-20 12:15:08 +01:00
|
|
|
*/
|
2020-01-30 17:02:02 +01:00
|
|
|
if (ASPEED_MACHINE(machine)->mmio_exec) {
|
hw/arm/aspeed: Remove extraneous MemoryRegion object owner
I'm confused by this code, 'bmc' is created as:
bmc = g_new0(AspeedBoardState, 1);
Then we use it as QOM owner for different MemoryRegion objects.
But looking at memory_region_init_ram (similarly for ROM):
void memory_region_init_ram(MemoryRegion *mr,
struct Object *owner,
const char *name,
uint64_t size,
Error **errp)
{
DeviceState *owner_dev;
Error *err = NULL;
memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
if (err) {
error_propagate(errp, err);
return;
}
/* This will assert if owner is neither NULL nor a DeviceState.
* We only want the owner here for the purposes of defining a
* unique name for migration. TODO: Ideally we should implement
* a naming scheme for Objects which are not DeviceStates, in
* which case we can relax this restriction.
*/
owner_dev = DEVICE(owner);
vmstate_register_ram(mr, owner_dev);
}
The expected assertion is not triggered ('bmc' is not NULL neither
a DeviceState).
'bmc' structure is defined as:
struct AspeedBoardState {
AspeedSoCState soc;
MemoryRegion ram_container;
MemoryRegion max_ram;
};
What happens is when using 'OBJECT(bmc)', the QOM macros cast the
memory pointed by bmc, which first member is 'soc', which is
initialized ...:
object_initialize_child(OBJECT(machine), "soc",
&bmc->soc, amc->soc_name);
The 'soc' object is indeed a DeviceState, so the assertion passes.
Since this is fragile and only happens to work by luck, remove the
dangerous OBJECT(bmc) owner argument.
Note, this probably breaks migration for this machine.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200623072132.2868-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-23 09:21:30 +02:00
|
|
|
memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom",
|
2020-01-30 17:02:02 +01:00
|
|
|
&fl->mmio, 0, fl->size);
|
|
|
|
memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
|
|
|
|
boot_rom);
|
|
|
|
} else {
|
hw/arm/aspeed: Remove extraneous MemoryRegion object owner
I'm confused by this code, 'bmc' is created as:
bmc = g_new0(AspeedBoardState, 1);
Then we use it as QOM owner for different MemoryRegion objects.
But looking at memory_region_init_ram (similarly for ROM):
void memory_region_init_ram(MemoryRegion *mr,
struct Object *owner,
const char *name,
uint64_t size,
Error **errp)
{
DeviceState *owner_dev;
Error *err = NULL;
memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
if (err) {
error_propagate(errp, err);
return;
}
/* This will assert if owner is neither NULL nor a DeviceState.
* We only want the owner here for the purposes of defining a
* unique name for migration. TODO: Ideally we should implement
* a naming scheme for Objects which are not DeviceStates, in
* which case we can relax this restriction.
*/
owner_dev = DEVICE(owner);
vmstate_register_ram(mr, owner_dev);
}
The expected assertion is not triggered ('bmc' is not NULL neither
a DeviceState).
'bmc' structure is defined as:
struct AspeedBoardState {
AspeedSoCState soc;
MemoryRegion ram_container;
MemoryRegion max_ram;
};
What happens is when using 'OBJECT(bmc)', the QOM macros cast the
memory pointed by bmc, which first member is 'soc', which is
initialized ...:
object_initialize_child(OBJECT(machine), "soc",
&bmc->soc, amc->soc_name);
The 'soc' object is indeed a DeviceState, so the assertion passes.
Since this is fragile and only happens to work by luck, remove the
dangerous OBJECT(bmc) owner argument.
Note, this probably breaks migration for this machine.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200623072132.2868-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-23 09:21:30 +02:00
|
|
|
memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom",
|
2020-01-30 17:02:02 +01:00
|
|
|
fl->size, &error_abort);
|
|
|
|
memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
|
|
|
|
boot_rom);
|
|
|
|
write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort);
|
|
|
|
}
|
2017-01-20 12:15:08 +01:00
|
|
|
}
|
|
|
|
|
arm/aspeed: Compute the number of CPUs from the SoC definition
Commit ece09beec457 ("aspeed: introduce a configurable number of CPU
per machine") was a convient change during bringup but the Aspeed SoCs
have a fixed number of CPUs : one for the AST2400 and AST2500, and two
for the AST2600.
When the number of CPUs configured with -smp is less than the SoC's
fixed number, the "unconfigured" CPUs are left unrealized. This can
happen for machines ast2600-evb and tacoma-bmc, where the SoC's fixed
number is 2. To get virtual hardware that matches the physical
hardware, you have to pass -smp cpus=2 (or its sugared form -smp 2).
We normally reject -smp cpus=N when N exceeds the machine's limit.
Except we ignore cpus=2 (and only cpus=2) with a warning for machines
ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc, swift-bmc, and
witherspoon-bmc.
Remove the "num-cpu" property from the SoC state and use the fixed
number of CPUs defined in the SoC class instead. Compute the default,
min, max number of CPUs of the machine directly from the SoC class
definition.
Machines ast2600-evb and tacoma-bmc now always get their second CPU as
they should. Visible in "info qom-tree"; here's the change for
ast2600-evb:
/machine (ast2600-evb-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
/a7mpcore (a15mpcore_priv)
/a15mp-priv-container[0] (qemu:memory-region)
/gic (arm_gic)
/gic_cpu[0] (qemu:memory-region)
/gic_cpu[1] (qemu:memory-region)
+ /gic_cpu[2] (qemu:memory-region)
/gic_dist[0] (qemu:memory-region)
/gic_vcpu[0] (qemu:memory-region)
/gic_viface[0] (qemu:memory-region)
/gic_viface[1] (qemu:memory-region)
+ /gic_viface[2] (qemu:memory-region)
/unnamed-gpio-in[0] (irq)
[...]
+ /unnamed-gpio-in[160] (irq)
[same for 161 to 190...]
+ /unnamed-gpio-in[191] (irq)
Also visible in "info qtree"; here's the change for ast2600-evb:
bus: main-system-bus
type System
dev: a15mpcore_priv, id ""
gpio-in "" 128
- gpio-out "sysbus-irq" 5
- num-cpu = 1 (0x1)
+ gpio-out "sysbus-irq" 10
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
mmio 0000000040460000/0000000000008000
dev: arm_gic, id ""
- gpio-in "" 160
- num-cpu = 1 (0x1)
+ gpio-in "" 192
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
revision = 2 (0x2)
has-security-extensions = true
has-virtualization-extensions = true
num-priority-bits = 8 (0x8)
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000200
mmio ffffffffffffffff/0000000000000200
The other machines now reject -smp cpus=2 just like -smp cpus=3 and up.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-5-armbru@redhat.com>
2020-06-09 14:23:19 +02:00
|
|
|
if (machine->kernel_filename && sc->num_cpus > 1) {
|
2020-04-09 08:31:37 +02:00
|
|
|
/* With no u-boot we must set up a boot stub for the secondary CPU */
|
|
|
|
MemoryRegion *smpboot = g_new(MemoryRegion, 1);
|
hw/arm/aspeed: Remove extraneous MemoryRegion object owner
I'm confused by this code, 'bmc' is created as:
bmc = g_new0(AspeedBoardState, 1);
Then we use it as QOM owner for different MemoryRegion objects.
But looking at memory_region_init_ram (similarly for ROM):
void memory_region_init_ram(MemoryRegion *mr,
struct Object *owner,
const char *name,
uint64_t size,
Error **errp)
{
DeviceState *owner_dev;
Error *err = NULL;
memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
if (err) {
error_propagate(errp, err);
return;
}
/* This will assert if owner is neither NULL nor a DeviceState.
* We only want the owner here for the purposes of defining a
* unique name for migration. TODO: Ideally we should implement
* a naming scheme for Objects which are not DeviceStates, in
* which case we can relax this restriction.
*/
owner_dev = DEVICE(owner);
vmstate_register_ram(mr, owner_dev);
}
The expected assertion is not triggered ('bmc' is not NULL neither
a DeviceState).
'bmc' structure is defined as:
struct AspeedBoardState {
AspeedSoCState soc;
MemoryRegion ram_container;
MemoryRegion max_ram;
};
What happens is when using 'OBJECT(bmc)', the QOM macros cast the
memory pointed by bmc, which first member is 'soc', which is
initialized ...:
object_initialize_child(OBJECT(machine), "soc",
&bmc->soc, amc->soc_name);
The 'soc' object is indeed a DeviceState, so the assertion passes.
Since this is fragile and only happens to work by luck, remove the
dangerous OBJECT(bmc) owner argument.
Note, this probably breaks migration for this machine.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200623072132.2868-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-23 09:21:30 +02:00
|
|
|
memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
|
2020-04-09 08:31:37 +02:00
|
|
|
0x80, &error_abort);
|
|
|
|
memory_region_add_subregion(get_system_memory(),
|
|
|
|
AST_SMP_MAILBOX_BASE, smpboot);
|
|
|
|
|
|
|
|
aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
|
|
|
|
aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
|
|
|
|
aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
|
|
|
|
}
|
|
|
|
|
2020-10-28 11:18:20 +01:00
|
|
|
aspeed_board_binfo.ram_size = machine->ram_size;
|
2020-08-25 21:20:02 +02:00
|
|
|
aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
|
arm/aspeed: Compute the number of CPUs from the SoC definition
Commit ece09beec457 ("aspeed: introduce a configurable number of CPU
per machine") was a convient change during bringup but the Aspeed SoCs
have a fixed number of CPUs : one for the AST2400 and AST2500, and two
for the AST2600.
When the number of CPUs configured with -smp is less than the SoC's
fixed number, the "unconfigured" CPUs are left unrealized. This can
happen for machines ast2600-evb and tacoma-bmc, where the SoC's fixed
number is 2. To get virtual hardware that matches the physical
hardware, you have to pass -smp cpus=2 (or its sugared form -smp 2).
We normally reject -smp cpus=N when N exceeds the machine's limit.
Except we ignore cpus=2 (and only cpus=2) with a warning for machines
ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc, swift-bmc, and
witherspoon-bmc.
Remove the "num-cpu" property from the SoC state and use the fixed
number of CPUs defined in the SoC class instead. Compute the default,
min, max number of CPUs of the machine directly from the SoC class
definition.
Machines ast2600-evb and tacoma-bmc now always get their second CPU as
they should. Visible in "info qom-tree"; here's the change for
ast2600-evb:
/machine (ast2600-evb-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
/a7mpcore (a15mpcore_priv)
/a15mp-priv-container[0] (qemu:memory-region)
/gic (arm_gic)
/gic_cpu[0] (qemu:memory-region)
/gic_cpu[1] (qemu:memory-region)
+ /gic_cpu[2] (qemu:memory-region)
/gic_dist[0] (qemu:memory-region)
/gic_vcpu[0] (qemu:memory-region)
/gic_viface[0] (qemu:memory-region)
/gic_viface[1] (qemu:memory-region)
+ /gic_viface[2] (qemu:memory-region)
/unnamed-gpio-in[0] (irq)
[...]
+ /unnamed-gpio-in[160] (irq)
[same for 161 to 190...]
+ /unnamed-gpio-in[191] (irq)
Also visible in "info qtree"; here's the change for ast2600-evb:
bus: main-system-bus
type System
dev: a15mpcore_priv, id ""
gpio-in "" 128
- gpio-out "sysbus-irq" 5
- num-cpu = 1 (0x1)
+ gpio-out "sysbus-irq" 10
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
mmio 0000000040460000/0000000000008000
dev: arm_gic, id ""
- gpio-in "" 160
- num-cpu = 1 (0x1)
+ gpio-in "" 192
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
revision = 2 (0x2)
has-security-extensions = true
has-virtualization-extensions = true
num-priority-bits = 8 (0x8)
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000200
mmio ffffffffffffffff/0000000000000200
The other machines now reject -smp cpus=2 just like -smp cpus=3 and up.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-5-armbru@redhat.com>
2020-06-09 14:23:19 +02:00
|
|
|
aspeed_board_binfo.nb_cpus = sc->num_cpus;
|
2016-07-04 14:06:38 +02:00
|
|
|
|
2019-11-19 15:12:07 +01:00
|
|
|
if (amc->i2c_init) {
|
|
|
|
amc->i2c_init(bmc);
|
2017-06-02 12:51:49 +02:00
|
|
|
}
|
|
|
|
|
2020-01-30 17:02:02 +01:00
|
|
|
for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
|
2020-01-30 17:02:02 +01:00
|
|
|
sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD));
|
|
|
|
}
|
2019-09-25 16:32:27 +02:00
|
|
|
|
2020-01-30 17:02:02 +01:00
|
|
|
if (bmc->soc.emmc.num_slots) {
|
|
|
|
sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD));
|
2019-09-25 16:32:27 +02:00
|
|
|
}
|
|
|
|
|
2019-08-09 08:57:21 +02:00
|
|
|
arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
|
2016-09-22 19:13:05 +02:00
|
|
|
}
|
2016-09-22 19:13:05 +02:00
|
|
|
|
2020-06-23 09:21:31 +02:00
|
|
|
static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
|
2017-06-02 12:51:49 +02:00
|
|
|
{
|
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
2017-06-13 15:56:59 +02:00
|
|
|
DeviceState *dev;
|
2018-06-08 14:15:32 +02:00
|
|
|
uint8_t *eeprom_buf = g_malloc0(32 * 1024);
|
2017-06-02 12:51:49 +02:00
|
|
|
|
|
|
|
/* The palmetto platform expects a ds3231 RTC but a ds1338 is
|
|
|
|
* enough to provide basic RTC features. Alarms will be missing */
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
|
2017-06-13 15:56:59 +02:00
|
|
|
|
2020-07-06 00:41:50 +02:00
|
|
|
smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
|
2018-06-08 14:15:32 +02:00
|
|
|
eeprom_buf);
|
|
|
|
|
2017-06-13 15:56:59 +02:00
|
|
|
/* add a TMP423 temperature sensor */
|
2020-07-06 00:41:53 +02:00
|
|
|
dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
|
|
|
|
"tmp423", 0x4c));
|
qom: Put name parameter before value / visitor parameter
The object_property_set_FOO() setters take property name and value in
an unusual order:
void object_property_set_FOO(Object *obj, FOO_TYPE value,
const char *name, Error **errp)
Having to pass value before name feels grating. Swap them.
Same for object_property_set(), object_property_get(), and
object_property_parse().
Convert callers with this Coccinelle script:
@@
identifier fun = {
object_property_get, object_property_parse, object_property_set_str,
object_property_set_link, object_property_set_bool,
object_property_set_int, object_property_set_uint, object_property_set,
object_property_set_qobject
};
expression obj, v, name, errp;
@@
- fun(obj, v, name, errp)
+ fun(obj, name, v, errp)
Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error
message "no position information". Convert that one manually.
Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by
ARMSSE being used both as typedef and function-like macro there.
Convert manually.
Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused
by RXCPU being used both as typedef and function-like macro there.
Convert manually. The other files using RXCPU that way don't need
conversion.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20200707160613.848843-27-armbru@redhat.com>
[Straightforwad conflict with commit 2336172d9b "audio: set default
value for pcspk.iobase property" resolved]
2020-07-07 18:05:54 +02:00
|
|
|
object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
|
|
|
|
object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
|
|
|
|
object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
|
|
|
|
object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
|
2017-06-02 12:51:49 +02:00
|
|
|
}
|
|
|
|
|
2021-05-01 10:03:52 +02:00
|
|
|
static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
|
|
|
|
{
|
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The quanta-q71l platform expects tmp75s which are compatible with
|
|
|
|
* tmp105s.
|
|
|
|
*/
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
|
|
|
|
|
|
|
|
/* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
|
|
|
|
/* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
|
|
|
|
/* TODO: Add Memory Riser i2c mux and eeproms. */
|
|
|
|
|
2021-06-08 22:25:22 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
|
|
|
|
|
2021-05-01 10:03:52 +02:00
|
|
|
/* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
|
2021-06-08 22:25:22 +02:00
|
|
|
|
|
|
|
/* i2c-7 */
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
|
2021-05-01 10:03:52 +02:00
|
|
|
/* - i2c@0: pmbus@59 */
|
|
|
|
/* - i2c@1: pmbus@58 */
|
|
|
|
/* - i2c@2: pmbus@58 */
|
|
|
|
/* - i2c@3: pmbus@59 */
|
2021-06-08 22:25:22 +02:00
|
|
|
|
2021-05-01 10:03:52 +02:00
|
|
|
/* TODO: i2c-7: Add PDB FRU eeprom@52 */
|
|
|
|
/* TODO: i2c-8: Add BMC FRU eeprom@50 */
|
|
|
|
}
|
|
|
|
|
2020-06-23 09:21:31 +02:00
|
|
|
static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
|
2017-06-02 12:51:49 +02:00
|
|
|
{
|
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
2018-06-08 14:15:32 +02:00
|
|
|
uint8_t *eeprom_buf = g_malloc0(8 * 1024);
|
|
|
|
|
2020-07-06 00:41:50 +02:00
|
|
|
smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
|
2018-06-08 14:15:32 +02:00
|
|
|
eeprom_buf);
|
2017-06-02 12:51:49 +02:00
|
|
|
|
|
|
|
/* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
|
2019-04-12 18:54:05 +02:00
|
|
|
TYPE_TMP105, 0x4d);
|
2018-06-08 14:15:32 +02:00
|
|
|
|
|
|
|
/* The AST2500 EVB does not have an RTC. Let's pretend that one is
|
|
|
|
* plugged on the I2C bus header */
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
|
2017-06-02 12:51:49 +02:00
|
|
|
}
|
|
|
|
|
2020-06-23 09:21:31 +02:00
|
|
|
static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
|
2019-10-23 15:04:55 +02:00
|
|
|
{
|
|
|
|
/* Start with some devices on our I2C busses */
|
|
|
|
ast2500_evb_i2c_init(bmc);
|
|
|
|
}
|
|
|
|
|
2020-06-23 09:21:31 +02:00
|
|
|
static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
|
2018-06-08 14:15:32 +02:00
|
|
|
{
|
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
|
|
|
|
|
|
|
/* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
|
|
|
|
* good enough */
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
|
2018-06-08 14:15:32 +02:00
|
|
|
}
|
|
|
|
|
2020-06-23 09:21:31 +02:00
|
|
|
static void swift_bmc_i2c_init(AspeedMachineState *bmc)
|
2019-07-01 18:26:17 +02:00
|
|
|
{
|
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
|
|
|
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x60);
|
2019-07-01 18:26:17 +02:00
|
|
|
|
|
|
|
/* The swift board expects a TMP275 but a TMP105 is compatible */
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "tmp105", 0x48);
|
2019-07-01 18:26:17 +02:00
|
|
|
/* The swift board expects a pca9551 but a pca9552 is compatible */
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60);
|
2019-07-01 18:26:17 +02:00
|
|
|
|
|
|
|
/* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "ds1338", 0x32);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
|
2019-07-01 18:26:17 +02:00
|
|
|
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
|
2019-07-01 18:26:17 +02:00
|
|
|
/* The swift board expects a pca9539 but a pca9552 is compatible */
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "pca9552", 0x74);
|
2019-07-01 18:26:17 +02:00
|
|
|
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
|
2019-07-01 18:26:17 +02:00
|
|
|
/* The swift board expects a pca9539 but a pca9552 is compatible */
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "pca9552",
|
2019-07-01 18:26:17 +02:00
|
|
|
0x74);
|
|
|
|
|
|
|
|
/* The swift board expects a TMP275 but a TMP105 is compatible */
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x48);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x4a);
|
2019-07-01 18:26:17 +02:00
|
|
|
}
|
|
|
|
|
2020-06-23 09:21:31 +02:00
|
|
|
static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
|
2020-05-06 20:32:19 +02:00
|
|
|
{
|
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
|
|
|
|
|
|
|
/* bus 2 : */
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
|
2020-05-06 20:32:19 +02:00
|
|
|
/* bus 2 : pca9546 @ 0x73 */
|
|
|
|
|
|
|
|
/* bus 3 : pca9548 @ 0x70 */
|
|
|
|
|
|
|
|
/* bus 4 : */
|
|
|
|
uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
|
2020-07-06 00:41:50 +02:00
|
|
|
smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
|
2020-05-06 20:32:19 +02:00
|
|
|
eeprom4_54);
|
|
|
|
/* PCA9539 @ 0x76, but PCA9552 is compatible */
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x76);
|
2020-05-06 20:32:19 +02:00
|
|
|
/* PCA9539 @ 0x77, but PCA9552 is compatible */
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x77);
|
2020-05-06 20:32:19 +02:00
|
|
|
|
|
|
|
/* bus 6 : */
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
|
2020-05-06 20:32:19 +02:00
|
|
|
/* bus 6 : pca9546 @ 0x73 */
|
|
|
|
|
|
|
|
/* bus 8 : */
|
|
|
|
uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
|
2020-07-06 00:41:50 +02:00
|
|
|
smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
|
2020-05-06 20:32:19 +02:00
|
|
|
eeprom8_56);
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61);
|
2020-05-06 20:32:19 +02:00
|
|
|
/* bus 8 : adc128d818 @ 0x1d */
|
|
|
|
/* bus 8 : adc128d818 @ 0x1f */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* bus 13 : pca9548 @ 0x71
|
|
|
|
* - channel 3:
|
|
|
|
* - tmm421 @ 0x4c
|
|
|
|
* - tmp421 @ 0x4e
|
|
|
|
* - tmp421 @ 0x4f
|
|
|
|
*/
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2020-06-23 09:21:31 +02:00
|
|
|
static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
|
2018-06-08 14:15:32 +02:00
|
|
|
{
|
2020-06-20 18:54:41 +02:00
|
|
|
static const struct {
|
|
|
|
unsigned gpio_id;
|
|
|
|
LEDColor color;
|
|
|
|
const char *description;
|
|
|
|
bool gpio_polarity;
|
|
|
|
} pca1_leds[] = {
|
|
|
|
{13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW},
|
|
|
|
{14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW},
|
|
|
|
{15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW},
|
|
|
|
};
|
2018-06-08 14:15:32 +02:00
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
2018-06-08 14:15:32 +02:00
|
|
|
uint8_t *eeprom_buf = g_malloc0(8 * 1024);
|
2020-06-23 09:27:21 +02:00
|
|
|
DeviceState *dev;
|
2020-06-20 18:54:41 +02:00
|
|
|
LEDState *led;
|
2018-06-08 14:15:32 +02:00
|
|
|
|
2019-11-19 15:12:08 +01:00
|
|
|
/* Bus 3: TODO bmp280@77 */
|
|
|
|
/* Bus 3: TODO max31785@52 */
|
|
|
|
/* Bus 3: TODO dps310@76 */
|
2020-07-06 00:41:51 +02:00
|
|
|
dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
|
2020-06-23 09:27:21 +02:00
|
|
|
qdev_prop_set_string(dev, "description", "pca1");
|
2020-07-06 00:41:52 +02:00
|
|
|
i2c_slave_realize_and_unref(I2C_SLAVE(dev),
|
|
|
|
aspeed_i2c_get_bus(&soc->i2c, 3),
|
|
|
|
&error_fatal);
|
2018-06-08 14:15:32 +02:00
|
|
|
|
2020-06-20 18:54:41 +02:00
|
|
|
for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
|
|
|
|
led = led_create_simple(OBJECT(bmc),
|
|
|
|
pca1_leds[i].gpio_polarity,
|
|
|
|
pca1_leds[i].color,
|
|
|
|
pca1_leds[i].description);
|
|
|
|
qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
|
|
|
|
qdev_get_gpio_in(DEVICE(led), 0));
|
|
|
|
}
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
|
2018-06-08 14:15:32 +02:00
|
|
|
|
|
|
|
/* The Witherspoon expects a TMP275 but a TMP105 is compatible */
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
|
2019-04-12 18:54:05 +02:00
|
|
|
0x4a);
|
2018-06-08 14:15:32 +02:00
|
|
|
|
|
|
|
/* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
|
|
|
|
* good enough */
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
|
2018-06-08 14:15:32 +02:00
|
|
|
|
2020-07-06 00:41:50 +02:00
|
|
|
smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
|
2018-06-08 14:15:32 +02:00
|
|
|
eeprom_buf);
|
2020-07-06 00:41:51 +02:00
|
|
|
dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
|
2020-06-23 09:27:21 +02:00
|
|
|
qdev_prop_set_string(dev, "description", "pca0");
|
2020-07-06 00:41:52 +02:00
|
|
|
i2c_slave_realize_and_unref(I2C_SLAVE(dev),
|
|
|
|
aspeed_i2c_get_bus(&soc->i2c, 11),
|
|
|
|
&error_fatal);
|
2019-11-19 15:12:08 +01:00
|
|
|
/* Bus 11: TODO ucd90160@64 */
|
2018-06-08 14:15:32 +02:00
|
|
|
}
|
|
|
|
|
2020-12-10 12:11:03 +01:00
|
|
|
static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
|
|
|
|
{
|
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
|
|
|
DeviceState *dev;
|
|
|
|
|
|
|
|
dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
|
|
|
|
"emc1413", 0x4c));
|
|
|
|
object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
|
|
|
|
object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
|
|
|
|
object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
|
|
|
|
|
|
|
|
dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
|
|
|
|
"emc1413", 0x4c));
|
|
|
|
object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
|
|
|
|
object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
|
|
|
|
object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
|
|
|
|
|
|
|
|
dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
|
|
|
|
"emc1413", 0x4c));
|
|
|
|
object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
|
|
|
|
object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
|
|
|
|
object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
|
2020-12-10 12:11:03 +01:00
|
|
|
|
|
|
|
static uint8_t eeprom_buf[2 * 1024] = {
|
|
|
|
0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
|
|
|
|
0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
|
|
|
|
0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
|
|
|
|
0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
|
|
|
|
0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
|
|
|
|
0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
|
|
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
|
|
|
|
};
|
|
|
|
smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
|
|
|
|
eeprom_buf);
|
2020-12-10 12:11:03 +01:00
|
|
|
}
|
|
|
|
|
2021-09-20 08:50:59 +02:00
|
|
|
static void aspeed_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
|
|
|
|
{
|
|
|
|
I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
|
|
|
|
DeviceState *dev = DEVICE(i2c_dev);
|
|
|
|
|
|
|
|
qdev_prop_set_uint32(dev, "rom-size", rsize);
|
|
|
|
i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
|
|
|
|
}
|
|
|
|
|
2021-05-01 10:03:52 +02:00
|
|
|
static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
|
|
|
|
{
|
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
2021-09-20 08:50:59 +02:00
|
|
|
I2CSlave *i2c_mux;
|
|
|
|
|
|
|
|
aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
|
2021-05-01 10:03:52 +02:00
|
|
|
|
|
|
|
/* The rainier expects a TMP275 but a TMP105 is compatible */
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
|
|
|
|
0x48);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
|
|
|
|
0x49);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
|
|
|
|
0x4a);
|
2021-09-20 08:50:59 +02:00
|
|
|
i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
|
|
|
|
"pca9546", 0x70);
|
|
|
|
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
|
|
|
|
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
|
|
|
|
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
|
2021-05-01 10:03:52 +02:00
|
|
|
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
|
|
|
|
0x48);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
|
|
|
|
0x49);
|
2021-09-20 08:50:59 +02:00
|
|
|
i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
|
|
|
|
"pca9546", 0x70);
|
|
|
|
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
|
|
|
|
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
|
2021-05-01 10:03:52 +02:00
|
|
|
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
|
|
|
|
0x48);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
|
|
|
|
0x4a);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
|
|
|
|
0x4b);
|
2021-09-20 08:50:59 +02:00
|
|
|
i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
|
|
|
|
"pca9546", 0x70);
|
|
|
|
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
|
|
|
|
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
|
|
|
|
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
|
|
|
|
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
|
2021-05-01 10:03:52 +02:00
|
|
|
|
|
|
|
/* Bus 7: TODO dps310@76 */
|
|
|
|
/* Bus 7: TODO max31785@52 */
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x61);
|
|
|
|
/* Bus 7: TODO si7021-a20@20 */
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
|
|
|
|
0x48);
|
2021-09-20 08:50:59 +02:00
|
|
|
aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
|
|
|
|
aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
|
2021-05-01 10:03:52 +02:00
|
|
|
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
|
|
|
|
0x48);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
|
|
|
|
0x4a);
|
2021-09-20 08:50:59 +02:00
|
|
|
aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
|
|
|
|
aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
|
2021-05-01 10:03:52 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61);
|
|
|
|
/* Bus 8: ucd90320@11 */
|
|
|
|
/* Bus 8: ucd90320@b */
|
|
|
|
/* Bus 8: ucd90320@c */
|
|
|
|
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
|
2021-09-20 08:50:59 +02:00
|
|
|
aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
|
2021-05-01 10:03:52 +02:00
|
|
|
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
|
2021-09-20 08:50:59 +02:00
|
|
|
aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
|
2021-05-01 10:03:52 +02:00
|
|
|
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
|
|
|
|
0x48);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
|
|
|
|
0x49);
|
2021-09-20 08:50:59 +02:00
|
|
|
i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
|
|
|
|
"pca9546", 0x70);
|
|
|
|
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
|
|
|
|
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
|
|
|
|
|
|
|
|
|
|
|
|
aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
|
|
|
|
|
|
|
|
aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
|
|
|
|
|
|
|
|
aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
|
2021-05-01 10:03:52 +02:00
|
|
|
}
|
|
|
|
|
2020-01-30 17:02:02 +01:00
|
|
|
static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
|
|
|
|
{
|
|
|
|
return ASPEED_MACHINE(obj)->mmio_exec;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
|
|
|
|
{
|
|
|
|
ASPEED_MACHINE(obj)->mmio_exec = value;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void aspeed_machine_instance_init(Object *obj)
|
|
|
|
{
|
|
|
|
ASPEED_MACHINE(obj)->mmio_exec = false;
|
|
|
|
}
|
|
|
|
|
2020-09-18 09:04:36 +02:00
|
|
|
static char *aspeed_get_fmc_model(Object *obj, Error **errp)
|
|
|
|
{
|
|
|
|
AspeedMachineState *bmc = ASPEED_MACHINE(obj);
|
|
|
|
return g_strdup(bmc->fmc_model);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
|
|
|
|
{
|
|
|
|
AspeedMachineState *bmc = ASPEED_MACHINE(obj);
|
|
|
|
|
|
|
|
g_free(bmc->fmc_model);
|
|
|
|
bmc->fmc_model = g_strdup(value);
|
|
|
|
}
|
|
|
|
|
|
|
|
static char *aspeed_get_spi_model(Object *obj, Error **errp)
|
|
|
|
{
|
|
|
|
AspeedMachineState *bmc = ASPEED_MACHINE(obj);
|
|
|
|
return g_strdup(bmc->spi_model);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
|
|
|
|
{
|
|
|
|
AspeedMachineState *bmc = ASPEED_MACHINE(obj);
|
|
|
|
|
|
|
|
g_free(bmc->spi_model);
|
|
|
|
bmc->spi_model = g_strdup(value);
|
|
|
|
}
|
|
|
|
|
2020-01-30 17:02:02 +01:00
|
|
|
static void aspeed_machine_class_props_init(ObjectClass *oc)
|
|
|
|
{
|
|
|
|
object_class_property_add_bool(oc, "execute-in-place",
|
|
|
|
aspeed_get_mmio_exec,
|
qom: Drop parameter @errp of object_property_add() & friends
The only way object_property_add() can fail is when a property with
the same name already exists. Since our property names are all
hardcoded, failure is a programming error, and the appropriate way to
handle it is passing &error_abort.
Same for its variants, except for object_property_add_child(), which
additionally fails when the child already has a parent. Parentage is
also under program control, so this is a programming error, too.
We have a bit over 500 callers. Almost half of them pass
&error_abort, slightly fewer ignore errors, one test case handles
errors, and the remaining few callers pass them to their own callers.
The previous few commits demonstrated once again that ignoring
programming errors is a bad idea.
Of the few ones that pass on errors, several violate the Error API.
The Error ** argument must be NULL, &error_abort, &error_fatal, or a
pointer to a variable containing NULL. Passing an argument of the
latter kind twice without clearing it in between is wrong: if the
first call sets an error, it no longer points to NULL for the second
call. ich9_pm_add_properties(), sparc32_ledma_realize(),
sparc32_dma_realize(), xilinx_axidma_realize(), xilinx_enet_realize()
are wrong that way.
When the one appropriate choice of argument is &error_abort, letting
users pick the argument is a bad idea.
Drop parameter @errp and assert the preconditions instead.
There's one exception to "duplicate property name is a programming
error": the way object_property_add() implements the magic (and
undocumented) "automatic arrayification". Don't drop @errp there.
Instead, rename object_property_add() to object_property_try_add(),
and add the obvious wrapper object_property_add().
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200505152926.18877-15-armbru@redhat.com>
[Two semantic rebase conflicts resolved]
2020-05-05 17:29:22 +02:00
|
|
|
aspeed_set_mmio_exec);
|
2020-01-30 17:02:02 +01:00
|
|
|
object_class_property_set_description(oc, "execute-in-place",
|
2020-05-05 17:29:15 +02:00
|
|
|
"boot directly from CE0 flash device");
|
2020-09-18 09:04:36 +02:00
|
|
|
|
|
|
|
object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
|
|
|
|
aspeed_set_fmc_model);
|
|
|
|
object_class_property_set_description(oc, "fmc-model",
|
|
|
|
"Change the FMC Flash model");
|
|
|
|
object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
|
|
|
|
aspeed_set_spi_model);
|
|
|
|
object_class_property_set_description(oc, "spi-model",
|
|
|
|
"Change the SPI Flash model");
|
2020-01-30 17:02:02 +01:00
|
|
|
}
|
|
|
|
|
arm/aspeed: Compute the number of CPUs from the SoC definition
Commit ece09beec457 ("aspeed: introduce a configurable number of CPU
per machine") was a convient change during bringup but the Aspeed SoCs
have a fixed number of CPUs : one for the AST2400 and AST2500, and two
for the AST2600.
When the number of CPUs configured with -smp is less than the SoC's
fixed number, the "unconfigured" CPUs are left unrealized. This can
happen for machines ast2600-evb and tacoma-bmc, where the SoC's fixed
number is 2. To get virtual hardware that matches the physical
hardware, you have to pass -smp cpus=2 (or its sugared form -smp 2).
We normally reject -smp cpus=N when N exceeds the machine's limit.
Except we ignore cpus=2 (and only cpus=2) with a warning for machines
ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc, swift-bmc, and
witherspoon-bmc.
Remove the "num-cpu" property from the SoC state and use the fixed
number of CPUs defined in the SoC class instead. Compute the default,
min, max number of CPUs of the machine directly from the SoC class
definition.
Machines ast2600-evb and tacoma-bmc now always get their second CPU as
they should. Visible in "info qom-tree"; here's the change for
ast2600-evb:
/machine (ast2600-evb-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
/a7mpcore (a15mpcore_priv)
/a15mp-priv-container[0] (qemu:memory-region)
/gic (arm_gic)
/gic_cpu[0] (qemu:memory-region)
/gic_cpu[1] (qemu:memory-region)
+ /gic_cpu[2] (qemu:memory-region)
/gic_dist[0] (qemu:memory-region)
/gic_vcpu[0] (qemu:memory-region)
/gic_viface[0] (qemu:memory-region)
/gic_viface[1] (qemu:memory-region)
+ /gic_viface[2] (qemu:memory-region)
/unnamed-gpio-in[0] (irq)
[...]
+ /unnamed-gpio-in[160] (irq)
[same for 161 to 190...]
+ /unnamed-gpio-in[191] (irq)
Also visible in "info qtree"; here's the change for ast2600-evb:
bus: main-system-bus
type System
dev: a15mpcore_priv, id ""
gpio-in "" 128
- gpio-out "sysbus-irq" 5
- num-cpu = 1 (0x1)
+ gpio-out "sysbus-irq" 10
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
mmio 0000000040460000/0000000000008000
dev: arm_gic, id ""
- gpio-in "" 160
- num-cpu = 1 (0x1)
+ gpio-in "" 192
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
revision = 2 (0x2)
has-security-extensions = true
has-virtualization-extensions = true
num-priority-bits = 8 (0x8)
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000200
mmio ffffffffffffffff/0000000000000200
The other machines now reject -smp cpus=2 just like -smp cpus=3 and up.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-5-armbru@redhat.com>
2020-06-09 14:23:19 +02:00
|
|
|
static int aspeed_soc_num_cpus(const char *soc_name)
|
|
|
|
{
|
|
|
|
AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
|
|
|
|
return sc->num_cpus;
|
|
|
|
}
|
|
|
|
|
2018-09-25 15:02:33 +02:00
|
|
|
static void aspeed_machine_class_init(ObjectClass *oc, void *data)
|
2018-06-08 14:15:32 +02:00
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
arm/aspeed: Rework NIC attachment
The number of MACs supported by an Aspeed SoC is defined by "macs_num"
under the SoC model, that is two for the AST2400 and AST2500 and four
for the AST2600. The model initializes the maximum number of supported
MACs but the number of realized devices is capped by the number of
network device back-ends defined on the command line. This can leave
unrealized devices hanging around in the QOM composition tree.
To get virtual hardware that matches the physical hardware, you have
to pass exactly as many -nic options as there are MACs, and some of
them must be -nic none:
* Machines ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc,
swift-bmc, and witherspoon-bmc: two -nic, and the second one must be
-nic none.
* Machine ast2600-evb: four -nic, the first one must be -nic none.
* Machine tacoma-bmc: four nic, the first two and the last one must be
-nic none.
Modify the machine initialization to define which MACs are attached to
a network device back-end using a bit-field property "macs-mask" and
let the SoC realize all network devices.
The default setting of "macs-mask" is "use MAC0" only, which works for
all our AST2400 and AST2500 machines. The AST2600 machines have
different configurations. The AST2600 EVB machine activates MAC1, MAC2
and MAC3 and the Tacoma BMC machine activates MAC2.
Incompatible CLI change: -nic options now apply to *active* MACs:
MAC1, MAC2, MAC3 for ast2600-evb, MAC2 for tacoma-bmc, and MAC0 for
all the others.
The machines now always get all MACs as they should. Visible in "info
qom-tree", here's the change for tacoma-bmc:
/machine (tacoma-bmc-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
[...]
/ftgmac100[0] (ftgmac100)
/ftgmac100[0] (qemu:memory-region)
/ftgmac100[1] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
/ftgmac100[2] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
/ftgmac100[3] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
[...]
/mii[0] (aspeed-mmi)
/aspeed-mmi[0] (qemu:memory-region)
/mii[1] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
/mii[2] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
/mii[3] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
Also visible in "info qtree"; here's the change for tacoma-bmc:
dev: ftgmac100, id ""
gpio-out "sysbus-irq" 1
aspeed = true
- mac = "52:54:00:12:34:56"
- netdev = "hub0port0"
+ mac = "52:54:00:12:34:57"
+ netdev = ""
mmio 000000001e660000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:58"
netdev = ""
+ mmio 000000001e680000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
- netdev = ""
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:56"
+ netdev = "hub0port0"
+ mmio 000000001e670000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:59"
netdev = ""
+ mmio 000000001e690000/0000000000002000
[...]
dev: aspeed-mmi, id ""
mmio 000000001e650000/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650008/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650010/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650018/0000000000000008
Inactive MACs will have no peer and QEMU may warn the user with :
qemu-system-arm: warning: nic ftgmac100.0 has no peer
qemu-system-arm: warning: nic ftgmac100.1 has no peer
qemu-system-arm: warning: nic ftgmac100.3 has no peer
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-6-armbru@redhat.com>
2020-06-09 14:23:20 +02:00
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
2018-06-08 14:15:32 +02:00
|
|
|
|
2018-09-25 15:02:33 +02:00
|
|
|
mc->init = aspeed_machine_init;
|
2018-06-08 14:15:32 +02:00
|
|
|
mc->no_floppy = 1;
|
|
|
|
mc->no_cdrom = 1;
|
|
|
|
mc->no_parallel = 1;
|
2020-02-19 17:08:44 +01:00
|
|
|
mc->default_ram_id = "ram";
|
arm/aspeed: Rework NIC attachment
The number of MACs supported by an Aspeed SoC is defined by "macs_num"
under the SoC model, that is two for the AST2400 and AST2500 and four
for the AST2600. The model initializes the maximum number of supported
MACs but the number of realized devices is capped by the number of
network device back-ends defined on the command line. This can leave
unrealized devices hanging around in the QOM composition tree.
To get virtual hardware that matches the physical hardware, you have
to pass exactly as many -nic options as there are MACs, and some of
them must be -nic none:
* Machines ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc,
swift-bmc, and witherspoon-bmc: two -nic, and the second one must be
-nic none.
* Machine ast2600-evb: four -nic, the first one must be -nic none.
* Machine tacoma-bmc: four nic, the first two and the last one must be
-nic none.
Modify the machine initialization to define which MACs are attached to
a network device back-end using a bit-field property "macs-mask" and
let the SoC realize all network devices.
The default setting of "macs-mask" is "use MAC0" only, which works for
all our AST2400 and AST2500 machines. The AST2600 machines have
different configurations. The AST2600 EVB machine activates MAC1, MAC2
and MAC3 and the Tacoma BMC machine activates MAC2.
Incompatible CLI change: -nic options now apply to *active* MACs:
MAC1, MAC2, MAC3 for ast2600-evb, MAC2 for tacoma-bmc, and MAC0 for
all the others.
The machines now always get all MACs as they should. Visible in "info
qom-tree", here's the change for tacoma-bmc:
/machine (tacoma-bmc-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
[...]
/ftgmac100[0] (ftgmac100)
/ftgmac100[0] (qemu:memory-region)
/ftgmac100[1] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
/ftgmac100[2] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
/ftgmac100[3] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
[...]
/mii[0] (aspeed-mmi)
/aspeed-mmi[0] (qemu:memory-region)
/mii[1] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
/mii[2] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
/mii[3] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
Also visible in "info qtree"; here's the change for tacoma-bmc:
dev: ftgmac100, id ""
gpio-out "sysbus-irq" 1
aspeed = true
- mac = "52:54:00:12:34:56"
- netdev = "hub0port0"
+ mac = "52:54:00:12:34:57"
+ netdev = ""
mmio 000000001e660000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:58"
netdev = ""
+ mmio 000000001e680000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
- netdev = ""
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:56"
+ netdev = "hub0port0"
+ mmio 000000001e670000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:59"
netdev = ""
+ mmio 000000001e690000/0000000000002000
[...]
dev: aspeed-mmi, id ""
mmio 000000001e650000/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650008/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650010/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650018/0000000000000008
Inactive MACs will have no peer and QEMU may warn the user with :
qemu-system-arm: warning: nic ftgmac100.0 has no peer
qemu-system-arm: warning: nic ftgmac100.1 has no peer
qemu-system-arm: warning: nic ftgmac100.3 has no peer
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-6-armbru@redhat.com>
2020-06-09 14:23:20 +02:00
|
|
|
amc->macs_mask = ASPEED_MAC0_ON;
|
2020-01-30 17:02:02 +01:00
|
|
|
|
|
|
|
aspeed_machine_class_props_init(oc);
|
2018-06-08 14:15:32 +02:00
|
|
|
}
|
|
|
|
|
2019-11-19 15:12:07 +01:00
|
|
|
static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
|
|
|
|
amc->soc_name = "ast2400-a1";
|
|
|
|
amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
|
|
|
|
amc->fmc_model = "n25q256a";
|
|
|
|
amc->spi_model = "mx25l25635e";
|
|
|
|
amc->num_cs = 1;
|
|
|
|
amc->i2c_init = palmetto_bmc_i2c_init;
|
|
|
|
mc->default_ram_size = 256 * MiB;
|
arm/aspeed: Compute the number of CPUs from the SoC definition
Commit ece09beec457 ("aspeed: introduce a configurable number of CPU
per machine") was a convient change during bringup but the Aspeed SoCs
have a fixed number of CPUs : one for the AST2400 and AST2500, and two
for the AST2600.
When the number of CPUs configured with -smp is less than the SoC's
fixed number, the "unconfigured" CPUs are left unrealized. This can
happen for machines ast2600-evb and tacoma-bmc, where the SoC's fixed
number is 2. To get virtual hardware that matches the physical
hardware, you have to pass -smp cpus=2 (or its sugared form -smp 2).
We normally reject -smp cpus=N when N exceeds the machine's limit.
Except we ignore cpus=2 (and only cpus=2) with a warning for machines
ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc, swift-bmc, and
witherspoon-bmc.
Remove the "num-cpu" property from the SoC state and use the fixed
number of CPUs defined in the SoC class instead. Compute the default,
min, max number of CPUs of the machine directly from the SoC class
definition.
Machines ast2600-evb and tacoma-bmc now always get their second CPU as
they should. Visible in "info qom-tree"; here's the change for
ast2600-evb:
/machine (ast2600-evb-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
/a7mpcore (a15mpcore_priv)
/a15mp-priv-container[0] (qemu:memory-region)
/gic (arm_gic)
/gic_cpu[0] (qemu:memory-region)
/gic_cpu[1] (qemu:memory-region)
+ /gic_cpu[2] (qemu:memory-region)
/gic_dist[0] (qemu:memory-region)
/gic_vcpu[0] (qemu:memory-region)
/gic_viface[0] (qemu:memory-region)
/gic_viface[1] (qemu:memory-region)
+ /gic_viface[2] (qemu:memory-region)
/unnamed-gpio-in[0] (irq)
[...]
+ /unnamed-gpio-in[160] (irq)
[same for 161 to 190...]
+ /unnamed-gpio-in[191] (irq)
Also visible in "info qtree"; here's the change for ast2600-evb:
bus: main-system-bus
type System
dev: a15mpcore_priv, id ""
gpio-in "" 128
- gpio-out "sysbus-irq" 5
- num-cpu = 1 (0x1)
+ gpio-out "sysbus-irq" 10
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
mmio 0000000040460000/0000000000008000
dev: arm_gic, id ""
- gpio-in "" 160
- num-cpu = 1 (0x1)
+ gpio-in "" 192
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
revision = 2 (0x2)
has-security-extensions = true
has-virtualization-extensions = true
num-priority-bits = 8 (0x8)
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000200
mmio ffffffffffffffff/0000000000000200
The other machines now reject -smp cpus=2 just like -smp cpus=3 and up.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-5-armbru@redhat.com>
2020-06-09 14:23:19 +02:00
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
2019-11-19 15:12:07 +01:00
|
|
|
};
|
|
|
|
|
2021-05-01 10:03:52 +02:00
|
|
|
static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)";
|
|
|
|
amc->soc_name = "ast2400-a1";
|
|
|
|
amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
|
|
|
|
amc->fmc_model = "n25q256a";
|
|
|
|
amc->spi_model = "mx25l25635e";
|
|
|
|
amc->num_cs = 1;
|
|
|
|
amc->i2c_init = quanta_q71l_bmc_i2c_init;
|
|
|
|
mc->default_ram_size = 128 * MiB;
|
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
|
|
|
}
|
|
|
|
|
2020-09-01 14:21:50 +02:00
|
|
|
static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
|
|
|
|
void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "Supermicro X11 BMC (ARM926EJ-S)";
|
|
|
|
amc->soc_name = "ast2400-a1";
|
|
|
|
amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
|
|
|
|
amc->fmc_model = "mx25l25635e";
|
|
|
|
amc->spi_model = "mx25l25635e";
|
|
|
|
amc->num_cs = 1;
|
|
|
|
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
|
|
|
|
amc->i2c_init = palmetto_bmc_i2c_init;
|
|
|
|
mc->default_ram_size = 256 * MiB;
|
|
|
|
}
|
|
|
|
|
2019-11-19 15:12:07 +01:00
|
|
|
static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "Aspeed AST2500 EVB (ARM1176)";
|
|
|
|
amc->soc_name = "ast2500-a1";
|
|
|
|
amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
|
|
|
|
amc->fmc_model = "w25q256";
|
|
|
|
amc->spi_model = "mx25l25635e";
|
|
|
|
amc->num_cs = 1;
|
|
|
|
amc->i2c_init = ast2500_evb_i2c_init;
|
|
|
|
mc->default_ram_size = 512 * MiB;
|
arm/aspeed: Compute the number of CPUs from the SoC definition
Commit ece09beec457 ("aspeed: introduce a configurable number of CPU
per machine") was a convient change during bringup but the Aspeed SoCs
have a fixed number of CPUs : one for the AST2400 and AST2500, and two
for the AST2600.
When the number of CPUs configured with -smp is less than the SoC's
fixed number, the "unconfigured" CPUs are left unrealized. This can
happen for machines ast2600-evb and tacoma-bmc, where the SoC's fixed
number is 2. To get virtual hardware that matches the physical
hardware, you have to pass -smp cpus=2 (or its sugared form -smp 2).
We normally reject -smp cpus=N when N exceeds the machine's limit.
Except we ignore cpus=2 (and only cpus=2) with a warning for machines
ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc, swift-bmc, and
witherspoon-bmc.
Remove the "num-cpu" property from the SoC state and use the fixed
number of CPUs defined in the SoC class instead. Compute the default,
min, max number of CPUs of the machine directly from the SoC class
definition.
Machines ast2600-evb and tacoma-bmc now always get their second CPU as
they should. Visible in "info qom-tree"; here's the change for
ast2600-evb:
/machine (ast2600-evb-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
/a7mpcore (a15mpcore_priv)
/a15mp-priv-container[0] (qemu:memory-region)
/gic (arm_gic)
/gic_cpu[0] (qemu:memory-region)
/gic_cpu[1] (qemu:memory-region)
+ /gic_cpu[2] (qemu:memory-region)
/gic_dist[0] (qemu:memory-region)
/gic_vcpu[0] (qemu:memory-region)
/gic_viface[0] (qemu:memory-region)
/gic_viface[1] (qemu:memory-region)
+ /gic_viface[2] (qemu:memory-region)
/unnamed-gpio-in[0] (irq)
[...]
+ /unnamed-gpio-in[160] (irq)
[same for 161 to 190...]
+ /unnamed-gpio-in[191] (irq)
Also visible in "info qtree"; here's the change for ast2600-evb:
bus: main-system-bus
type System
dev: a15mpcore_priv, id ""
gpio-in "" 128
- gpio-out "sysbus-irq" 5
- num-cpu = 1 (0x1)
+ gpio-out "sysbus-irq" 10
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
mmio 0000000040460000/0000000000008000
dev: arm_gic, id ""
- gpio-in "" 160
- num-cpu = 1 (0x1)
+ gpio-in "" 192
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
revision = 2 (0x2)
has-security-extensions = true
has-virtualization-extensions = true
num-priority-bits = 8 (0x8)
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000200
mmio ffffffffffffffff/0000000000000200
The other machines now reject -smp cpus=2 just like -smp cpus=3 and up.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-5-armbru@redhat.com>
2020-06-09 14:23:19 +02:00
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
2019-11-19 15:12:07 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
|
|
|
|
amc->soc_name = "ast2500-a1";
|
|
|
|
amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
|
|
|
|
amc->fmc_model = "n25q256a";
|
|
|
|
amc->spi_model = "mx66l1g45g";
|
|
|
|
amc->num_cs = 2;
|
|
|
|
amc->i2c_init = romulus_bmc_i2c_init;
|
|
|
|
mc->default_ram_size = 512 * MiB;
|
arm/aspeed: Compute the number of CPUs from the SoC definition
Commit ece09beec457 ("aspeed: introduce a configurable number of CPU
per machine") was a convient change during bringup but the Aspeed SoCs
have a fixed number of CPUs : one for the AST2400 and AST2500, and two
for the AST2600.
When the number of CPUs configured with -smp is less than the SoC's
fixed number, the "unconfigured" CPUs are left unrealized. This can
happen for machines ast2600-evb and tacoma-bmc, where the SoC's fixed
number is 2. To get virtual hardware that matches the physical
hardware, you have to pass -smp cpus=2 (or its sugared form -smp 2).
We normally reject -smp cpus=N when N exceeds the machine's limit.
Except we ignore cpus=2 (and only cpus=2) with a warning for machines
ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc, swift-bmc, and
witherspoon-bmc.
Remove the "num-cpu" property from the SoC state and use the fixed
number of CPUs defined in the SoC class instead. Compute the default,
min, max number of CPUs of the machine directly from the SoC class
definition.
Machines ast2600-evb and tacoma-bmc now always get their second CPU as
they should. Visible in "info qom-tree"; here's the change for
ast2600-evb:
/machine (ast2600-evb-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
/a7mpcore (a15mpcore_priv)
/a15mp-priv-container[0] (qemu:memory-region)
/gic (arm_gic)
/gic_cpu[0] (qemu:memory-region)
/gic_cpu[1] (qemu:memory-region)
+ /gic_cpu[2] (qemu:memory-region)
/gic_dist[0] (qemu:memory-region)
/gic_vcpu[0] (qemu:memory-region)
/gic_viface[0] (qemu:memory-region)
/gic_viface[1] (qemu:memory-region)
+ /gic_viface[2] (qemu:memory-region)
/unnamed-gpio-in[0] (irq)
[...]
+ /unnamed-gpio-in[160] (irq)
[same for 161 to 190...]
+ /unnamed-gpio-in[191] (irq)
Also visible in "info qtree"; here's the change for ast2600-evb:
bus: main-system-bus
type System
dev: a15mpcore_priv, id ""
gpio-in "" 128
- gpio-out "sysbus-irq" 5
- num-cpu = 1 (0x1)
+ gpio-out "sysbus-irq" 10
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
mmio 0000000040460000/0000000000008000
dev: arm_gic, id ""
- gpio-in "" 160
- num-cpu = 1 (0x1)
+ gpio-in "" 192
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
revision = 2 (0x2)
has-security-extensions = true
has-virtualization-extensions = true
num-priority-bits = 8 (0x8)
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000200
mmio ffffffffffffffff/0000000000000200
The other machines now reject -smp cpus=2 just like -smp cpus=3 and up.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-5-armbru@redhat.com>
2020-06-09 14:23:19 +02:00
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
2018-09-25 15:02:33 +02:00
|
|
|
};
|
|
|
|
|
2020-05-06 20:32:19 +02:00
|
|
|
static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "OCP SonoraPass BMC (ARM1176)";
|
|
|
|
amc->soc_name = "ast2500-a1";
|
|
|
|
amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
|
|
|
|
amc->fmc_model = "mx66l1g45g";
|
|
|
|
amc->spi_model = "mx66l1g45g";
|
|
|
|
amc->num_cs = 2;
|
|
|
|
amc->i2c_init = sonorapass_bmc_i2c_init;
|
|
|
|
mc->default_ram_size = 512 * MiB;
|
arm/aspeed: Compute the number of CPUs from the SoC definition
Commit ece09beec457 ("aspeed: introduce a configurable number of CPU
per machine") was a convient change during bringup but the Aspeed SoCs
have a fixed number of CPUs : one for the AST2400 and AST2500, and two
for the AST2600.
When the number of CPUs configured with -smp is less than the SoC's
fixed number, the "unconfigured" CPUs are left unrealized. This can
happen for machines ast2600-evb and tacoma-bmc, where the SoC's fixed
number is 2. To get virtual hardware that matches the physical
hardware, you have to pass -smp cpus=2 (or its sugared form -smp 2).
We normally reject -smp cpus=N when N exceeds the machine's limit.
Except we ignore cpus=2 (and only cpus=2) with a warning for machines
ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc, swift-bmc, and
witherspoon-bmc.
Remove the "num-cpu" property from the SoC state and use the fixed
number of CPUs defined in the SoC class instead. Compute the default,
min, max number of CPUs of the machine directly from the SoC class
definition.
Machines ast2600-evb and tacoma-bmc now always get their second CPU as
they should. Visible in "info qom-tree"; here's the change for
ast2600-evb:
/machine (ast2600-evb-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
/a7mpcore (a15mpcore_priv)
/a15mp-priv-container[0] (qemu:memory-region)
/gic (arm_gic)
/gic_cpu[0] (qemu:memory-region)
/gic_cpu[1] (qemu:memory-region)
+ /gic_cpu[2] (qemu:memory-region)
/gic_dist[0] (qemu:memory-region)
/gic_vcpu[0] (qemu:memory-region)
/gic_viface[0] (qemu:memory-region)
/gic_viface[1] (qemu:memory-region)
+ /gic_viface[2] (qemu:memory-region)
/unnamed-gpio-in[0] (irq)
[...]
+ /unnamed-gpio-in[160] (irq)
[same for 161 to 190...]
+ /unnamed-gpio-in[191] (irq)
Also visible in "info qtree"; here's the change for ast2600-evb:
bus: main-system-bus
type System
dev: a15mpcore_priv, id ""
gpio-in "" 128
- gpio-out "sysbus-irq" 5
- num-cpu = 1 (0x1)
+ gpio-out "sysbus-irq" 10
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
mmio 0000000040460000/0000000000008000
dev: arm_gic, id ""
- gpio-in "" 160
- num-cpu = 1 (0x1)
+ gpio-in "" 192
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
revision = 2 (0x2)
has-security-extensions = true
has-virtualization-extensions = true
num-priority-bits = 8 (0x8)
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000200
mmio ffffffffffffffff/0000000000000200
The other machines now reject -smp cpus=2 just like -smp cpus=3 and up.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-5-armbru@redhat.com>
2020-06-09 14:23:19 +02:00
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
2020-05-06 20:32:19 +02:00
|
|
|
};
|
|
|
|
|
2019-11-19 15:12:07 +01:00
|
|
|
static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "OpenPOWER Swift BMC (ARM1176)";
|
|
|
|
amc->soc_name = "ast2500-a1";
|
|
|
|
amc->hw_strap1 = SWIFT_BMC_HW_STRAP1;
|
|
|
|
amc->fmc_model = "mx66l1g45g";
|
|
|
|
amc->spi_model = "mx66l1g45g";
|
|
|
|
amc->num_cs = 2;
|
|
|
|
amc->i2c_init = swift_bmc_i2c_init;
|
|
|
|
mc->default_ram_size = 512 * MiB;
|
arm/aspeed: Compute the number of CPUs from the SoC definition
Commit ece09beec457 ("aspeed: introduce a configurable number of CPU
per machine") was a convient change during bringup but the Aspeed SoCs
have a fixed number of CPUs : one for the AST2400 and AST2500, and two
for the AST2600.
When the number of CPUs configured with -smp is less than the SoC's
fixed number, the "unconfigured" CPUs are left unrealized. This can
happen for machines ast2600-evb and tacoma-bmc, where the SoC's fixed
number is 2. To get virtual hardware that matches the physical
hardware, you have to pass -smp cpus=2 (or its sugared form -smp 2).
We normally reject -smp cpus=N when N exceeds the machine's limit.
Except we ignore cpus=2 (and only cpus=2) with a warning for machines
ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc, swift-bmc, and
witherspoon-bmc.
Remove the "num-cpu" property from the SoC state and use the fixed
number of CPUs defined in the SoC class instead. Compute the default,
min, max number of CPUs of the machine directly from the SoC class
definition.
Machines ast2600-evb and tacoma-bmc now always get their second CPU as
they should. Visible in "info qom-tree"; here's the change for
ast2600-evb:
/machine (ast2600-evb-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
/a7mpcore (a15mpcore_priv)
/a15mp-priv-container[0] (qemu:memory-region)
/gic (arm_gic)
/gic_cpu[0] (qemu:memory-region)
/gic_cpu[1] (qemu:memory-region)
+ /gic_cpu[2] (qemu:memory-region)
/gic_dist[0] (qemu:memory-region)
/gic_vcpu[0] (qemu:memory-region)
/gic_viface[0] (qemu:memory-region)
/gic_viface[1] (qemu:memory-region)
+ /gic_viface[2] (qemu:memory-region)
/unnamed-gpio-in[0] (irq)
[...]
+ /unnamed-gpio-in[160] (irq)
[same for 161 to 190...]
+ /unnamed-gpio-in[191] (irq)
Also visible in "info qtree"; here's the change for ast2600-evb:
bus: main-system-bus
type System
dev: a15mpcore_priv, id ""
gpio-in "" 128
- gpio-out "sysbus-irq" 5
- num-cpu = 1 (0x1)
+ gpio-out "sysbus-irq" 10
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
mmio 0000000040460000/0000000000008000
dev: arm_gic, id ""
- gpio-in "" 160
- num-cpu = 1 (0x1)
+ gpio-in "" 192
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
revision = 2 (0x2)
has-security-extensions = true
has-virtualization-extensions = true
num-priority-bits = 8 (0x8)
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000200
mmio ffffffffffffffff/0000000000000200
The other machines now reject -smp cpus=2 just like -smp cpus=3 and up.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-5-armbru@redhat.com>
2020-06-09 14:23:19 +02:00
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
2021-05-01 10:03:52 +02:00
|
|
|
|
|
|
|
mc->deprecation_reason = "redundant system. Please use a similar "
|
|
|
|
"OpenPOWER BMC, Witherspoon or Romulus.";
|
2019-11-19 15:12:07 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
|
|
|
|
amc->soc_name = "ast2500-a1";
|
|
|
|
amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
|
|
|
|
amc->fmc_model = "mx25l25635e";
|
|
|
|
amc->spi_model = "mx66l1g45g";
|
|
|
|
amc->num_cs = 2;
|
|
|
|
amc->i2c_init = witherspoon_bmc_i2c_init;
|
|
|
|
mc->default_ram_size = 512 * MiB;
|
arm/aspeed: Compute the number of CPUs from the SoC definition
Commit ece09beec457 ("aspeed: introduce a configurable number of CPU
per machine") was a convient change during bringup but the Aspeed SoCs
have a fixed number of CPUs : one for the AST2400 and AST2500, and two
for the AST2600.
When the number of CPUs configured with -smp is less than the SoC's
fixed number, the "unconfigured" CPUs are left unrealized. This can
happen for machines ast2600-evb and tacoma-bmc, where the SoC's fixed
number is 2. To get virtual hardware that matches the physical
hardware, you have to pass -smp cpus=2 (or its sugared form -smp 2).
We normally reject -smp cpus=N when N exceeds the machine's limit.
Except we ignore cpus=2 (and only cpus=2) with a warning for machines
ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc, swift-bmc, and
witherspoon-bmc.
Remove the "num-cpu" property from the SoC state and use the fixed
number of CPUs defined in the SoC class instead. Compute the default,
min, max number of CPUs of the machine directly from the SoC class
definition.
Machines ast2600-evb and tacoma-bmc now always get their second CPU as
they should. Visible in "info qom-tree"; here's the change for
ast2600-evb:
/machine (ast2600-evb-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
/a7mpcore (a15mpcore_priv)
/a15mp-priv-container[0] (qemu:memory-region)
/gic (arm_gic)
/gic_cpu[0] (qemu:memory-region)
/gic_cpu[1] (qemu:memory-region)
+ /gic_cpu[2] (qemu:memory-region)
/gic_dist[0] (qemu:memory-region)
/gic_vcpu[0] (qemu:memory-region)
/gic_viface[0] (qemu:memory-region)
/gic_viface[1] (qemu:memory-region)
+ /gic_viface[2] (qemu:memory-region)
/unnamed-gpio-in[0] (irq)
[...]
+ /unnamed-gpio-in[160] (irq)
[same for 161 to 190...]
+ /unnamed-gpio-in[191] (irq)
Also visible in "info qtree"; here's the change for ast2600-evb:
bus: main-system-bus
type System
dev: a15mpcore_priv, id ""
gpio-in "" 128
- gpio-out "sysbus-irq" 5
- num-cpu = 1 (0x1)
+ gpio-out "sysbus-irq" 10
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
mmio 0000000040460000/0000000000008000
dev: arm_gic, id ""
- gpio-in "" 160
- num-cpu = 1 (0x1)
+ gpio-in "" 192
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
revision = 2 (0x2)
has-security-extensions = true
has-virtualization-extensions = true
num-priority-bits = 8 (0x8)
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000200
mmio ffffffffffffffff/0000000000000200
The other machines now reject -smp cpus=2 just like -smp cpus=3 and up.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-5-armbru@redhat.com>
2020-06-09 14:23:19 +02:00
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
2019-11-19 15:12:07 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
2021-05-27 11:51:52 +02:00
|
|
|
mc->desc = "Aspeed AST2600 EVB (Cortex-A7)";
|
2020-05-04 11:37:03 +02:00
|
|
|
amc->soc_name = "ast2600-a1";
|
2019-11-19 15:12:07 +01:00
|
|
|
amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
|
|
|
|
amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
|
|
|
|
amc->fmc_model = "w25q512jv";
|
|
|
|
amc->spi_model = "mx66u51235f";
|
|
|
|
amc->num_cs = 1;
|
2021-09-20 08:50:59 +02:00
|
|
|
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
|
|
|
|
ASPEED_MAC3_ON;
|
2019-11-19 15:12:07 +01:00
|
|
|
amc->i2c_init = ast2600_evb_i2c_init;
|
|
|
|
mc->default_ram_size = 1 * GiB;
|
arm/aspeed: Compute the number of CPUs from the SoC definition
Commit ece09beec457 ("aspeed: introduce a configurable number of CPU
per machine") was a convient change during bringup but the Aspeed SoCs
have a fixed number of CPUs : one for the AST2400 and AST2500, and two
for the AST2600.
When the number of CPUs configured with -smp is less than the SoC's
fixed number, the "unconfigured" CPUs are left unrealized. This can
happen for machines ast2600-evb and tacoma-bmc, where the SoC's fixed
number is 2. To get virtual hardware that matches the physical
hardware, you have to pass -smp cpus=2 (or its sugared form -smp 2).
We normally reject -smp cpus=N when N exceeds the machine's limit.
Except we ignore cpus=2 (and only cpus=2) with a warning for machines
ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc, swift-bmc, and
witherspoon-bmc.
Remove the "num-cpu" property from the SoC state and use the fixed
number of CPUs defined in the SoC class instead. Compute the default,
min, max number of CPUs of the machine directly from the SoC class
definition.
Machines ast2600-evb and tacoma-bmc now always get their second CPU as
they should. Visible in "info qom-tree"; here's the change for
ast2600-evb:
/machine (ast2600-evb-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
/a7mpcore (a15mpcore_priv)
/a15mp-priv-container[0] (qemu:memory-region)
/gic (arm_gic)
/gic_cpu[0] (qemu:memory-region)
/gic_cpu[1] (qemu:memory-region)
+ /gic_cpu[2] (qemu:memory-region)
/gic_dist[0] (qemu:memory-region)
/gic_vcpu[0] (qemu:memory-region)
/gic_viface[0] (qemu:memory-region)
/gic_viface[1] (qemu:memory-region)
+ /gic_viface[2] (qemu:memory-region)
/unnamed-gpio-in[0] (irq)
[...]
+ /unnamed-gpio-in[160] (irq)
[same for 161 to 190...]
+ /unnamed-gpio-in[191] (irq)
Also visible in "info qtree"; here's the change for ast2600-evb:
bus: main-system-bus
type System
dev: a15mpcore_priv, id ""
gpio-in "" 128
- gpio-out "sysbus-irq" 5
- num-cpu = 1 (0x1)
+ gpio-out "sysbus-irq" 10
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
mmio 0000000040460000/0000000000008000
dev: arm_gic, id ""
- gpio-in "" 160
- num-cpu = 1 (0x1)
+ gpio-in "" 192
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
revision = 2 (0x2)
has-security-extensions = true
has-virtualization-extensions = true
num-priority-bits = 8 (0x8)
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000200
mmio ffffffffffffffff/0000000000000200
The other machines now reject -smp cpus=2 just like -smp cpus=3 and up.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-5-armbru@redhat.com>
2020-06-09 14:23:19 +02:00
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
2019-11-19 15:12:07 +01:00
|
|
|
};
|
|
|
|
|
2019-11-19 15:12:08 +01:00
|
|
|
static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
2021-05-27 11:51:52 +02:00
|
|
|
mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)";
|
2020-05-04 11:37:03 +02:00
|
|
|
amc->soc_name = "ast2600-a1";
|
2019-11-19 15:12:08 +01:00
|
|
|
amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
|
|
|
|
amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
|
|
|
|
amc->fmc_model = "mx66l1g45g";
|
|
|
|
amc->spi_model = "mx66l1g45g";
|
|
|
|
amc->num_cs = 2;
|
arm/aspeed: Rework NIC attachment
The number of MACs supported by an Aspeed SoC is defined by "macs_num"
under the SoC model, that is two for the AST2400 and AST2500 and four
for the AST2600. The model initializes the maximum number of supported
MACs but the number of realized devices is capped by the number of
network device back-ends defined on the command line. This can leave
unrealized devices hanging around in the QOM composition tree.
To get virtual hardware that matches the physical hardware, you have
to pass exactly as many -nic options as there are MACs, and some of
them must be -nic none:
* Machines ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc,
swift-bmc, and witherspoon-bmc: two -nic, and the second one must be
-nic none.
* Machine ast2600-evb: four -nic, the first one must be -nic none.
* Machine tacoma-bmc: four nic, the first two and the last one must be
-nic none.
Modify the machine initialization to define which MACs are attached to
a network device back-end using a bit-field property "macs-mask" and
let the SoC realize all network devices.
The default setting of "macs-mask" is "use MAC0" only, which works for
all our AST2400 and AST2500 machines. The AST2600 machines have
different configurations. The AST2600 EVB machine activates MAC1, MAC2
and MAC3 and the Tacoma BMC machine activates MAC2.
Incompatible CLI change: -nic options now apply to *active* MACs:
MAC1, MAC2, MAC3 for ast2600-evb, MAC2 for tacoma-bmc, and MAC0 for
all the others.
The machines now always get all MACs as they should. Visible in "info
qom-tree", here's the change for tacoma-bmc:
/machine (tacoma-bmc-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
[...]
/ftgmac100[0] (ftgmac100)
/ftgmac100[0] (qemu:memory-region)
/ftgmac100[1] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
/ftgmac100[2] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
/ftgmac100[3] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
[...]
/mii[0] (aspeed-mmi)
/aspeed-mmi[0] (qemu:memory-region)
/mii[1] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
/mii[2] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
/mii[3] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
Also visible in "info qtree"; here's the change for tacoma-bmc:
dev: ftgmac100, id ""
gpio-out "sysbus-irq" 1
aspeed = true
- mac = "52:54:00:12:34:56"
- netdev = "hub0port0"
+ mac = "52:54:00:12:34:57"
+ netdev = ""
mmio 000000001e660000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:58"
netdev = ""
+ mmio 000000001e680000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
- netdev = ""
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:56"
+ netdev = "hub0port0"
+ mmio 000000001e670000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:59"
netdev = ""
+ mmio 000000001e690000/0000000000002000
[...]
dev: aspeed-mmi, id ""
mmio 000000001e650000/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650008/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650010/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650018/0000000000000008
Inactive MACs will have no peer and QEMU may warn the user with :
qemu-system-arm: warning: nic ftgmac100.0 has no peer
qemu-system-arm: warning: nic ftgmac100.1 has no peer
qemu-system-arm: warning: nic ftgmac100.3 has no peer
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-6-armbru@redhat.com>
2020-06-09 14:23:20 +02:00
|
|
|
amc->macs_mask = ASPEED_MAC2_ON;
|
2019-11-19 15:12:08 +01:00
|
|
|
amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
|
|
|
|
mc->default_ram_size = 1 * GiB;
|
arm/aspeed: Compute the number of CPUs from the SoC definition
Commit ece09beec457 ("aspeed: introduce a configurable number of CPU
per machine") was a convient change during bringup but the Aspeed SoCs
have a fixed number of CPUs : one for the AST2400 and AST2500, and two
for the AST2600.
When the number of CPUs configured with -smp is less than the SoC's
fixed number, the "unconfigured" CPUs are left unrealized. This can
happen for machines ast2600-evb and tacoma-bmc, where the SoC's fixed
number is 2. To get virtual hardware that matches the physical
hardware, you have to pass -smp cpus=2 (or its sugared form -smp 2).
We normally reject -smp cpus=N when N exceeds the machine's limit.
Except we ignore cpus=2 (and only cpus=2) with a warning for machines
ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc, swift-bmc, and
witherspoon-bmc.
Remove the "num-cpu" property from the SoC state and use the fixed
number of CPUs defined in the SoC class instead. Compute the default,
min, max number of CPUs of the machine directly from the SoC class
definition.
Machines ast2600-evb and tacoma-bmc now always get their second CPU as
they should. Visible in "info qom-tree"; here's the change for
ast2600-evb:
/machine (ast2600-evb-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
/a7mpcore (a15mpcore_priv)
/a15mp-priv-container[0] (qemu:memory-region)
/gic (arm_gic)
/gic_cpu[0] (qemu:memory-region)
/gic_cpu[1] (qemu:memory-region)
+ /gic_cpu[2] (qemu:memory-region)
/gic_dist[0] (qemu:memory-region)
/gic_vcpu[0] (qemu:memory-region)
/gic_viface[0] (qemu:memory-region)
/gic_viface[1] (qemu:memory-region)
+ /gic_viface[2] (qemu:memory-region)
/unnamed-gpio-in[0] (irq)
[...]
+ /unnamed-gpio-in[160] (irq)
[same for 161 to 190...]
+ /unnamed-gpio-in[191] (irq)
Also visible in "info qtree"; here's the change for ast2600-evb:
bus: main-system-bus
type System
dev: a15mpcore_priv, id ""
gpio-in "" 128
- gpio-out "sysbus-irq" 5
- num-cpu = 1 (0x1)
+ gpio-out "sysbus-irq" 10
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
mmio 0000000040460000/0000000000008000
dev: arm_gic, id ""
- gpio-in "" 160
- num-cpu = 1 (0x1)
+ gpio-in "" 192
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
revision = 2 (0x2)
has-security-extensions = true
has-virtualization-extensions = true
num-priority-bits = 8 (0x8)
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000200
mmio ffffffffffffffff/0000000000000200
The other machines now reject -smp cpus=2 just like -smp cpus=3 and up.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-5-armbru@redhat.com>
2020-06-09 14:23:19 +02:00
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
2019-11-19 15:12:08 +01:00
|
|
|
};
|
|
|
|
|
2020-12-10 12:11:03 +01:00
|
|
|
static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "Bytedance G220A BMC (ARM1176)";
|
|
|
|
amc->soc_name = "ast2500-a1";
|
|
|
|
amc->hw_strap1 = G220A_BMC_HW_STRAP1;
|
|
|
|
amc->fmc_model = "n25q512a";
|
|
|
|
amc->spi_model = "mx25l25635e";
|
|
|
|
amc->num_cs = 2;
|
2021-09-20 08:50:59 +02:00
|
|
|
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
|
2020-12-10 12:11:03 +01:00
|
|
|
amc->i2c_init = g220a_bmc_i2c_init;
|
|
|
|
mc->default_ram_size = 1024 * MiB;
|
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
|
|
|
};
|
|
|
|
|
2021-05-01 10:03:52 +02:00
|
|
|
static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
2021-05-27 11:51:52 +02:00
|
|
|
mc->desc = "IBM Rainier BMC (Cortex-A7)";
|
2021-05-01 10:03:52 +02:00
|
|
|
amc->soc_name = "ast2600-a1";
|
|
|
|
amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
|
|
|
|
amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
|
|
|
|
amc->fmc_model = "mx66l1g45g";
|
|
|
|
amc->spi_model = "mx66l1g45g";
|
|
|
|
amc->num_cs = 2;
|
|
|
|
amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
|
|
|
|
amc->i2c_init = rainier_bmc_i2c_init;
|
|
|
|
mc->default_ram_size = 1 * GiB;
|
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
|
|
|
};
|
|
|
|
|
2019-11-19 15:12:07 +01:00
|
|
|
static const TypeInfo aspeed_machine_types[] = {
|
2018-09-25 15:02:33 +02:00
|
|
|
{
|
2019-11-19 15:12:07 +01:00
|
|
|
.name = MACHINE_TYPE_NAME("palmetto-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_palmetto_class_init,
|
2020-09-01 14:21:50 +02:00
|
|
|
}, {
|
|
|
|
.name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_supermicrox11_bmc_class_init,
|
2018-09-25 15:02:33 +02:00
|
|
|
}, {
|
2019-11-19 15:12:07 +01:00
|
|
|
.name = MACHINE_TYPE_NAME("ast2500-evb"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_ast2500_evb_class_init,
|
2018-09-25 15:02:33 +02:00
|
|
|
}, {
|
2019-11-19 15:12:07 +01:00
|
|
|
.name = MACHINE_TYPE_NAME("romulus-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_romulus_class_init,
|
2019-07-01 18:26:17 +02:00
|
|
|
}, {
|
2019-11-19 15:12:07 +01:00
|
|
|
.name = MACHINE_TYPE_NAME("swift-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_swift_class_init,
|
2020-05-06 20:32:19 +02:00
|
|
|
}, {
|
|
|
|
.name = MACHINE_TYPE_NAME("sonorapass-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_sonorapass_class_init,
|
2018-09-25 15:02:33 +02:00
|
|
|
}, {
|
2019-11-19 15:12:07 +01:00
|
|
|
.name = MACHINE_TYPE_NAME("witherspoon-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_witherspoon_class_init,
|
2019-10-23 15:04:55 +02:00
|
|
|
}, {
|
2019-11-19 15:12:07 +01:00
|
|
|
.name = MACHINE_TYPE_NAME("ast2600-evb"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_ast2600_evb_class_init,
|
2019-11-19 15:12:08 +01:00
|
|
|
}, {
|
|
|
|
.name = MACHINE_TYPE_NAME("tacoma-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_tacoma_class_init,
|
2020-12-10 12:11:03 +01:00
|
|
|
}, {
|
|
|
|
.name = MACHINE_TYPE_NAME("g220a-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_g220a_class_init,
|
2021-05-01 10:03:52 +02:00
|
|
|
}, {
|
|
|
|
.name = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_quanta_q71l_class_init,
|
2021-05-01 10:03:52 +02:00
|
|
|
}, {
|
|
|
|
.name = MACHINE_TYPE_NAME("rainier-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_rainier_class_init,
|
2019-11-19 15:12:07 +01:00
|
|
|
}, {
|
|
|
|
.name = TYPE_ASPEED_MACHINE,
|
|
|
|
.parent = TYPE_MACHINE,
|
2020-06-23 09:21:32 +02:00
|
|
|
.instance_size = sizeof(AspeedMachineState),
|
2020-01-30 17:02:02 +01:00
|
|
|
.instance_init = aspeed_machine_instance_init,
|
2019-11-19 15:12:07 +01:00
|
|
|
.class_size = sizeof(AspeedMachineClass),
|
|
|
|
.class_init = aspeed_machine_class_init,
|
|
|
|
.abstract = true,
|
2018-09-25 15:02:33 +02:00
|
|
|
}
|
2019-11-19 15:12:07 +01:00
|
|
|
};
|
2016-09-22 19:13:05 +02:00
|
|
|
|
2019-11-19 15:12:07 +01:00
|
|
|
DEFINE_TYPES(aspeed_machine_types)
|