2008-04-14 23:57:44 +02:00
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|
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/*
|
|
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* OneNAND flash memories emulation.
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*
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* Copyright (C) 2008 Nokia Corporation
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* Written by Andrzej Zaborowski <andrew@openedhand.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
|
2009-01-04 23:05:52 +01:00
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* You should have received a copy of the GNU General Public License along
|
2009-07-16 22:47:01 +02:00
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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2008-04-14 23:57:44 +02:00
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*/
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2016-01-18 19:01:42 +01:00
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#include "qemu/osdep.h"
|
include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 09:01:28 +01:00
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#include "qapi/error.h"
|
2008-04-14 23:57:44 +02:00
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|
#include "qemu-common.h"
|
2013-02-04 15:40:22 +01:00
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|
#include "hw/hw.h"
|
2013-02-05 17:06:20 +01:00
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#include "hw/block/flash.h"
|
2013-02-04 15:40:22 +01:00
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#include "hw/irq.h"
|
2014-10-07 13:59:18 +02:00
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#include "sysemu/block-backend.h"
|
2012-12-17 18:19:49 +01:00
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|
#include "exec/memory.h"
|
2013-02-04 15:40:22 +01:00
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#include "hw/sysbus.h"
|
2012-12-17 18:20:00 +01:00
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#include "qemu/error-report.h"
|
2008-04-14 23:57:44 +02:00
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/* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
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#define PAGE_SHIFT 11
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|
/* Fixed */
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|
|
#define BLOCK_SHIFT (PAGE_SHIFT + 6)
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|
2013-07-24 10:44:48 +02:00
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#define TYPE_ONE_NAND "onenand"
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|
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#define ONE_NAND(obj) OBJECT_CHECK(OneNANDState, (obj), TYPE_ONE_NAND)
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typedef struct OneNANDState {
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SysBusDevice parent_obj;
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|
2011-07-29 17:35:26 +02:00
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struct {
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|
|
uint16_t man;
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uint16_t dev;
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uint16_t ver;
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} id;
|
2008-04-14 23:57:44 +02:00
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int shift;
|
2012-10-23 12:30:10 +02:00
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|
hwaddr base;
|
2008-04-14 23:57:44 +02:00
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qemu_irq intr;
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qemu_irq rdy;
|
2014-10-07 13:59:18 +02:00
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|
BlockBackend *blk;
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|
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BlockBackend *blk_cur;
|
2008-04-14 23:57:44 +02:00
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uint8_t *image;
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uint8_t *otp;
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uint8_t *current;
|
2011-08-15 16:17:24 +02:00
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MemoryRegion ram;
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|
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MemoryRegion mapped_ram;
|
2011-08-28 18:22:17 +02:00
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uint8_t current_direction;
|
2008-04-14 23:57:44 +02:00
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uint8_t *boot[2];
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|
uint8_t *data[2][2];
|
2011-08-15 16:17:24 +02:00
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MemoryRegion iomem;
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|
|
MemoryRegion container;
|
2008-04-14 23:57:44 +02:00
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int cycle;
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int otpmode;
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uint16_t addr[8];
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uint16_t unladdr[8];
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int bufaddr;
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int count;
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|
uint16_t command;
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uint16_t config[2];
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|
uint16_t status;
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|
uint16_t intstatus;
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|
uint16_t wpstatus;
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|
2009-05-10 02:44:56 +02:00
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|
ECCState ecc;
|
2008-04-14 23:57:44 +02:00
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|
|
int density_mask;
|
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|
int secs;
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|
|
int secs_cur;
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|
|
int blocks;
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|
|
uint8_t *blockwp;
|
2009-05-10 02:44:56 +02:00
|
|
|
} OneNANDState;
|
2008-04-14 23:57:44 +02:00
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enum {
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|
ONEN_BUF_BLOCK = 0,
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ONEN_BUF_BLOCK2 = 1,
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ONEN_BUF_DEST_BLOCK = 2,
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|
ONEN_BUF_DEST_PAGE = 3,
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|
ONEN_BUF_PAGE = 7,
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};
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enum {
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ONEN_ERR_CMD = 1 << 10,
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ONEN_ERR_ERASE = 1 << 11,
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ONEN_ERR_PROG = 1 << 12,
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ONEN_ERR_LOAD = 1 << 13,
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};
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enum {
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ONEN_INT_RESET = 1 << 4,
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ONEN_INT_ERASE = 1 << 5,
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ONEN_INT_PROG = 1 << 6,
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ONEN_INT_LOAD = 1 << 7,
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ONEN_INT = 1 << 15,
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|
};
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enum {
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ONEN_LOCK_LOCKTIGHTEN = 1 << 0,
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ONEN_LOCK_LOCKED = 1 << 1,
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ONEN_LOCK_UNLOCKED = 1 << 2,
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};
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|
2011-08-15 16:17:24 +02:00
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static void onenand_mem_setup(OneNANDState *s)
|
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|
|
{
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|
|
/* XXX: We should use IO_MEM_ROMD but we broke it earlier...
|
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* Both 0x0000 ... 0x01ff and 0x8000 ... 0x800f can be used to
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|
|
* write boot commands. Also take note of the BWPS bit. */
|
2013-06-07 03:25:08 +02:00
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memory_region_init(&s->container, OBJECT(s), "onenand",
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0x10000 << s->shift);
|
2011-08-15 16:17:24 +02:00
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memory_region_add_subregion(&s->container, 0, &s->iomem);
|
2013-06-07 03:25:08 +02:00
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memory_region_init_alias(&s->mapped_ram, OBJECT(s), "onenand-mapped-ram",
|
2011-08-15 16:17:24 +02:00
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&s->ram, 0x0200 << s->shift,
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0xbe00 << s->shift);
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memory_region_add_subregion_overlap(&s->container,
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0x0200 << s->shift,
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&s->mapped_ram,
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1);
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}
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|
2011-08-28 18:22:17 +02:00
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static void onenand_intr_update(OneNANDState *s)
|
2008-04-14 23:57:44 +02:00
|
|
|
{
|
2011-08-28 18:22:17 +02:00
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|
qemu_set_irq(s->intr, ((s->intstatus >> 15) ^ (~s->config[0] >> 6)) & 1);
|
2008-04-14 23:57:44 +02:00
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|
}
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|
2017-09-25 13:29:12 +02:00
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static int onenand_pre_save(void *opaque)
|
2008-04-14 23:57:44 +02:00
|
|
|
{
|
2011-08-28 18:22:17 +02:00
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OneNANDState *s = opaque;
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if (s->current == s->otp) {
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s->current_direction = 1;
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} else if (s->current == s->image) {
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s->current_direction = 2;
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|
} else {
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s->current_direction = 0;
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}
|
2017-09-25 13:29:12 +02:00
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return 0;
|
2008-04-14 23:57:44 +02:00
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}
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|
2011-08-28 18:22:17 +02:00
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static int onenand_post_load(void *opaque, int version_id)
|
2008-04-14 23:57:44 +02:00
|
|
|
{
|
2011-08-28 18:22:17 +02:00
|
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|
OneNANDState *s = opaque;
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switch (s->current_direction) {
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case 0:
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break;
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case 1:
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s->current = s->otp;
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break;
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case 2:
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s->current = s->image;
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break;
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default:
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|
return -1;
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}
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onenand_intr_update(s);
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|
return 0;
|
2008-04-14 23:57:44 +02:00
|
|
|
}
|
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|
2011-08-28 18:22:17 +02:00
|
|
|
static const VMStateDescription vmstate_onenand = {
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|
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.name = "onenand",
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|
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.version_id = 1,
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.minimum_version_id = 1,
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.pre_save = onenand_pre_save,
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.post_load = onenand_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(current_direction, OneNANDState),
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VMSTATE_INT32(cycle, OneNANDState),
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VMSTATE_INT32(otpmode, OneNANDState),
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VMSTATE_UINT16_ARRAY(addr, OneNANDState, 8),
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VMSTATE_UINT16_ARRAY(unladdr, OneNANDState, 8),
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VMSTATE_INT32(bufaddr, OneNANDState),
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VMSTATE_INT32(count, OneNANDState),
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VMSTATE_UINT16(command, OneNANDState),
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VMSTATE_UINT16_ARRAY(config, OneNANDState, 2),
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VMSTATE_UINT16(status, OneNANDState),
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VMSTATE_UINT16(intstatus, OneNANDState),
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VMSTATE_UINT16(wpstatus, OneNANDState),
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VMSTATE_INT32(secs_cur, OneNANDState),
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VMSTATE_PARTIAL_VBUFFER(blockwp, OneNANDState, blocks),
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VMSTATE_UINT8(ecc.cp, OneNANDState),
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|
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VMSTATE_UINT16_ARRAY(ecc.lp, OneNANDState, 2),
|
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|
|
VMSTATE_UINT16(ecc.count, OneNANDState),
|
2013-04-05 17:17:59 +02:00
|
|
|
VMSTATE_BUFFER_POINTER_UNSAFE(otp, OneNANDState, 0,
|
|
|
|
((64 + 2) << PAGE_SHIFT)),
|
2011-08-28 18:22:17 +02:00
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
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|
|
};
|
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|
|
2008-04-14 23:57:44 +02:00
|
|
|
/* Hot reset (Reset OneNAND command) or warm reset (RP pin low) */
|
2009-05-10 02:44:56 +02:00
|
|
|
static void onenand_reset(OneNANDState *s, int cold)
|
2008-04-14 23:57:44 +02:00
|
|
|
{
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|
|
|
memset(&s->addr, 0, sizeof(s->addr));
|
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|
|
s->command = 0;
|
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|
|
s->count = 1;
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|
|
s->bufaddr = 0;
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|
|
s->config[0] = 0x40c0;
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|
|
s->config[1] = 0x0000;
|
|
|
|
onenand_intr_update(s);
|
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|
|
qemu_irq_raise(s->rdy);
|
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|
|
s->status = 0x0000;
|
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|
|
s->intstatus = cold ? 0x8080 : 0x8010;
|
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|
|
s->unladdr[0] = 0;
|
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|
|
s->unladdr[1] = 0;
|
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|
|
s->wpstatus = 0x0002;
|
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|
|
s->cycle = 0;
|
|
|
|
s->otpmode = 0;
|
2014-10-07 13:59:18 +02:00
|
|
|
s->blk_cur = s->blk;
|
2008-04-14 23:57:44 +02:00
|
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|
s->current = s->image;
|
|
|
|
s->secs_cur = s->secs;
|
|
|
|
|
|
|
|
if (cold) {
|
|
|
|
/* Lock the whole flash */
|
|
|
|
memset(s->blockwp, ONEN_LOCK_LOCKED, s->blocks);
|
|
|
|
|
2016-05-06 18:26:37 +02:00
|
|
|
if (s->blk_cur && blk_pread(s->blk_cur, 0, s->boot[0],
|
|
|
|
8 << BDRV_SECTOR_BITS) < 0) {
|
2011-08-28 18:22:17 +02:00
|
|
|
hw_error("%s: Loading the BootRAM failed.\n", __func__);
|
|
|
|
}
|
2008-04-14 23:57:44 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-08-28 18:22:17 +02:00
|
|
|
static void onenand_system_reset(DeviceState *dev)
|
|
|
|
{
|
2013-07-24 10:44:48 +02:00
|
|
|
OneNANDState *s = ONE_NAND(dev);
|
|
|
|
|
|
|
|
onenand_reset(s, 1);
|
2011-08-28 18:22:17 +02:00
|
|
|
}
|
|
|
|
|
2009-05-10 02:44:56 +02:00
|
|
|
static inline int onenand_load_main(OneNANDState *s, int sec, int secn,
|
2008-04-14 23:57:44 +02:00
|
|
|
void *dest)
|
|
|
|
{
|
2016-05-06 18:26:37 +02:00
|
|
|
assert(UINT32_MAX >> BDRV_SECTOR_BITS > sec);
|
|
|
|
assert(UINT32_MAX >> BDRV_SECTOR_BITS > secn);
|
2014-10-07 13:59:18 +02:00
|
|
|
if (s->blk_cur) {
|
2016-05-06 18:26:37 +02:00
|
|
|
return blk_pread(s->blk_cur, sec << BDRV_SECTOR_BITS, dest,
|
|
|
|
secn << BDRV_SECTOR_BITS) < 0;
|
2014-10-07 13:59:18 +02:00
|
|
|
} else if (sec + secn > s->secs_cur) {
|
2008-04-14 23:57:44 +02:00
|
|
|
return 1;
|
2014-10-07 13:59:18 +02:00
|
|
|
}
|
2008-04-14 23:57:44 +02:00
|
|
|
|
|
|
|
memcpy(dest, s->current + (sec << 9), secn << 9);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-05-10 02:44:56 +02:00
|
|
|
static inline int onenand_prog_main(OneNANDState *s, int sec, int secn,
|
2008-04-14 23:57:44 +02:00
|
|
|
void *src)
|
|
|
|
{
|
2011-07-29 17:35:28 +02:00
|
|
|
int result = 0;
|
|
|
|
|
|
|
|
if (secn > 0) {
|
2016-05-06 18:26:37 +02:00
|
|
|
uint32_t size = secn << BDRV_SECTOR_BITS;
|
|
|
|
uint32_t offset = sec << BDRV_SECTOR_BITS;
|
|
|
|
assert(UINT32_MAX >> BDRV_SECTOR_BITS > sec);
|
|
|
|
assert(UINT32_MAX >> BDRV_SECTOR_BITS > secn);
|
2011-08-28 18:22:17 +02:00
|
|
|
const uint8_t *sp = (const uint8_t *)src;
|
2011-07-29 17:35:28 +02:00
|
|
|
uint8_t *dp = 0;
|
2014-10-07 13:59:18 +02:00
|
|
|
if (s->blk_cur) {
|
2011-08-21 05:09:37 +02:00
|
|
|
dp = g_malloc(size);
|
2016-05-06 18:26:37 +02:00
|
|
|
if (!dp || blk_pread(s->blk_cur, offset, dp, size) < 0) {
|
2011-07-29 17:35:28 +02:00
|
|
|
result = 1;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (sec + secn > s->secs_cur) {
|
|
|
|
result = 1;
|
|
|
|
} else {
|
2016-05-06 18:26:37 +02:00
|
|
|
dp = (uint8_t *)s->current + offset;
|
2011-07-29 17:35:28 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
if (!result) {
|
|
|
|
uint32_t i;
|
|
|
|
for (i = 0; i < size; i++) {
|
|
|
|
dp[i] &= sp[i];
|
|
|
|
}
|
2014-10-07 13:59:18 +02:00
|
|
|
if (s->blk_cur) {
|
2016-05-06 18:26:37 +02:00
|
|
|
result = blk_pwrite(s->blk_cur, offset, dp, size, 0) < 0;
|
2011-07-29 17:35:28 +02:00
|
|
|
}
|
|
|
|
}
|
2014-10-07 13:59:18 +02:00
|
|
|
if (dp && s->blk_cur) {
|
2011-08-21 05:09:37 +02:00
|
|
|
g_free(dp);
|
2011-07-29 17:35:28 +02:00
|
|
|
}
|
|
|
|
}
|
2008-04-14 23:57:44 +02:00
|
|
|
|
2011-07-29 17:35:28 +02:00
|
|
|
return result;
|
2008-04-14 23:57:44 +02:00
|
|
|
}
|
|
|
|
|
2009-05-10 02:44:56 +02:00
|
|
|
static inline int onenand_load_spare(OneNANDState *s, int sec, int secn,
|
2008-04-14 23:57:44 +02:00
|
|
|
void *dest)
|
|
|
|
{
|
|
|
|
uint8_t buf[512];
|
|
|
|
|
2014-10-07 13:59:18 +02:00
|
|
|
if (s->blk_cur) {
|
2016-05-06 18:26:37 +02:00
|
|
|
uint32_t offset = (s->secs_cur + (sec >> 5)) << BDRV_SECTOR_BITS;
|
|
|
|
if (blk_pread(s->blk_cur, offset, buf, BDRV_SECTOR_SIZE) < 0) {
|
2008-04-14 23:57:44 +02:00
|
|
|
return 1;
|
2014-10-07 13:59:18 +02:00
|
|
|
}
|
2008-04-14 23:57:44 +02:00
|
|
|
memcpy(dest, buf + ((sec & 31) << 4), secn << 4);
|
2014-10-07 13:59:18 +02:00
|
|
|
} else if (sec + secn > s->secs_cur) {
|
2008-04-14 23:57:44 +02:00
|
|
|
return 1;
|
2014-10-07 13:59:18 +02:00
|
|
|
} else {
|
2008-04-14 23:57:44 +02:00
|
|
|
memcpy(dest, s->current + (s->secs_cur << 9) + (sec << 4), secn << 4);
|
2014-10-07 13:59:18 +02:00
|
|
|
}
|
2016-05-06 18:26:37 +02:00
|
|
|
|
2008-04-14 23:57:44 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-05-10 02:44:56 +02:00
|
|
|
static inline int onenand_prog_spare(OneNANDState *s, int sec, int secn,
|
2008-04-14 23:57:44 +02:00
|
|
|
void *src)
|
|
|
|
{
|
2011-07-29 17:35:28 +02:00
|
|
|
int result = 0;
|
|
|
|
if (secn > 0) {
|
2011-08-28 18:22:17 +02:00
|
|
|
const uint8_t *sp = (const uint8_t *)src;
|
2011-07-29 17:35:28 +02:00
|
|
|
uint8_t *dp = 0, *dpp = 0;
|
2016-05-06 18:26:37 +02:00
|
|
|
uint32_t offset = (s->secs_cur + (sec >> 5)) << BDRV_SECTOR_BITS;
|
|
|
|
assert(UINT32_MAX >> BDRV_SECTOR_BITS > s->secs_cur + (sec >> 5));
|
2014-10-07 13:59:18 +02:00
|
|
|
if (s->blk_cur) {
|
2011-08-21 05:09:37 +02:00
|
|
|
dp = g_malloc(512);
|
2014-10-07 13:59:18 +02:00
|
|
|
if (!dp
|
2016-05-06 18:26:37 +02:00
|
|
|
|| blk_pread(s->blk_cur, offset, dp, BDRV_SECTOR_SIZE) < 0) {
|
2011-07-29 17:35:28 +02:00
|
|
|
result = 1;
|
|
|
|
} else {
|
|
|
|
dpp = dp + ((sec & 31) << 4);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (sec + secn > s->secs_cur) {
|
|
|
|
result = 1;
|
|
|
|
} else {
|
|
|
|
dpp = s->current + (s->secs_cur << 9) + (sec << 4);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (!result) {
|
|
|
|
uint32_t i;
|
|
|
|
for (i = 0; i < (secn << 4); i++) {
|
|
|
|
dpp[i] &= sp[i];
|
|
|
|
}
|
2014-10-07 13:59:18 +02:00
|
|
|
if (s->blk_cur) {
|
2016-05-06 18:26:37 +02:00
|
|
|
result = blk_pwrite(s->blk_cur, offset, dp,
|
|
|
|
BDRV_SECTOR_SIZE, 0) < 0;
|
2011-07-29 17:35:28 +02:00
|
|
|
}
|
|
|
|
}
|
2014-06-06 18:25:12 +02:00
|
|
|
g_free(dp);
|
2011-07-29 17:35:28 +02:00
|
|
|
}
|
|
|
|
return result;
|
2008-04-14 23:57:44 +02:00
|
|
|
}
|
|
|
|
|
2009-05-10 02:44:56 +02:00
|
|
|
static inline int onenand_erase(OneNANDState *s, int sec, int num)
|
2008-04-14 23:57:44 +02:00
|
|
|
{
|
2011-07-29 17:35:28 +02:00
|
|
|
uint8_t *blankbuf, *tmpbuf;
|
2015-02-04 11:26:02 +01:00
|
|
|
|
2011-08-21 05:09:37 +02:00
|
|
|
blankbuf = g_malloc(512);
|
|
|
|
tmpbuf = g_malloc(512);
|
2011-07-29 17:35:28 +02:00
|
|
|
memset(blankbuf, 0xff, 512);
|
|
|
|
for (; num > 0; num--, sec++) {
|
2014-10-07 13:59:18 +02:00
|
|
|
if (s->blk_cur) {
|
2011-07-29 17:35:28 +02:00
|
|
|
int erasesec = s->secs_cur + (sec >> 5);
|
2016-05-06 18:26:37 +02:00
|
|
|
if (blk_pwrite(s->blk_cur, sec << BDRV_SECTOR_BITS, blankbuf,
|
|
|
|
BDRV_SECTOR_SIZE, 0) < 0) {
|
2011-07-29 17:35:28 +02:00
|
|
|
goto fail;
|
|
|
|
}
|
2016-05-06 18:26:37 +02:00
|
|
|
if (blk_pread(s->blk_cur, erasesec << BDRV_SECTOR_BITS, tmpbuf,
|
|
|
|
BDRV_SECTOR_SIZE) < 0) {
|
2011-07-29 17:35:28 +02:00
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
memcpy(tmpbuf + ((sec & 31) << 4), blankbuf, 1 << 4);
|
2016-05-06 18:26:37 +02:00
|
|
|
if (blk_pwrite(s->blk_cur, erasesec << BDRV_SECTOR_BITS, tmpbuf,
|
|
|
|
BDRV_SECTOR_SIZE, 0) < 0) {
|
2011-07-29 17:35:28 +02:00
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (sec + 1 > s->secs_cur) {
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
memcpy(s->current + (sec << 9), blankbuf, 512);
|
|
|
|
memcpy(s->current + (s->secs_cur << 9) + (sec << 4),
|
|
|
|
blankbuf, 1 << 4);
|
|
|
|
}
|
2008-04-14 23:57:44 +02:00
|
|
|
}
|
|
|
|
|
2011-08-21 05:09:37 +02:00
|
|
|
g_free(tmpbuf);
|
|
|
|
g_free(blankbuf);
|
2008-04-14 23:57:44 +02:00
|
|
|
return 0;
|
2011-07-29 17:35:28 +02:00
|
|
|
|
|
|
|
fail:
|
2011-08-21 05:09:37 +02:00
|
|
|
g_free(tmpbuf);
|
|
|
|
g_free(blankbuf);
|
2011-07-29 17:35:28 +02:00
|
|
|
return 1;
|
2008-04-14 23:57:44 +02:00
|
|
|
}
|
|
|
|
|
2011-08-28 18:33:02 +02:00
|
|
|
static void onenand_command(OneNANDState *s)
|
2008-04-14 23:57:44 +02:00
|
|
|
{
|
|
|
|
int b;
|
|
|
|
int sec;
|
|
|
|
void *buf;
|
|
|
|
#define SETADDR(block, page) \
|
|
|
|
sec = (s->addr[page] & 3) + \
|
|
|
|
((((s->addr[page] >> 2) & 0x3f) + \
|
|
|
|
(((s->addr[block] & 0xfff) | \
|
|
|
|
(s->addr[block] >> 15 ? \
|
|
|
|
s->density_mask : 0)) << 6)) << (PAGE_SHIFT - 9));
|
|
|
|
#define SETBUF_M() \
|
|
|
|
buf = (s->bufaddr & 8) ? \
|
|
|
|
s->data[(s->bufaddr >> 2) & 1][0] : s->boot[0]; \
|
|
|
|
buf += (s->bufaddr & 3) << 9;
|
|
|
|
#define SETBUF_S() \
|
|
|
|
buf = (s->bufaddr & 8) ? \
|
|
|
|
s->data[(s->bufaddr >> 2) & 1][1] : s->boot[1]; \
|
|
|
|
buf += (s->bufaddr & 3) << 4;
|
|
|
|
|
2011-08-28 18:33:02 +02:00
|
|
|
switch (s->command) {
|
2008-04-14 23:57:44 +02:00
|
|
|
case 0x00: /* Load single/multiple sector data unit into buffer */
|
|
|
|
SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
|
|
|
|
|
|
|
|
SETBUF_M()
|
|
|
|
if (onenand_load_main(s, sec, s->count, buf))
|
|
|
|
s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD;
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
SETBUF_S()
|
|
|
|
if (onenand_load_spare(s, sec, s->count, buf))
|
|
|
|
s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
|
|
|
|
* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
|
|
|
|
* then we need two split the read/write into two chunks.
|
|
|
|
*/
|
|
|
|
s->intstatus |= ONEN_INT | ONEN_INT_LOAD;
|
|
|
|
break;
|
|
|
|
case 0x13: /* Load single/multiple spare sector into buffer */
|
|
|
|
SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
|
|
|
|
|
|
|
|
SETBUF_S()
|
|
|
|
if (onenand_load_spare(s, sec, s->count, buf))
|
|
|
|
s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD;
|
|
|
|
|
|
|
|
/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
|
|
|
|
* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
|
|
|
|
* then we need two split the read/write into two chunks.
|
|
|
|
*/
|
|
|
|
s->intstatus |= ONEN_INT | ONEN_INT_LOAD;
|
|
|
|
break;
|
|
|
|
case 0x80: /* Program single/multiple sector data unit from buffer */
|
|
|
|
SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
|
|
|
|
|
|
|
|
SETBUF_M()
|
|
|
|
if (onenand_prog_main(s, sec, s->count, buf))
|
|
|
|
s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG;
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
SETBUF_S()
|
|
|
|
if (onenand_prog_spare(s, sec, s->count, buf))
|
|
|
|
s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
|
|
|
|
* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
|
|
|
|
* then we need two split the read/write into two chunks.
|
|
|
|
*/
|
|
|
|
s->intstatus |= ONEN_INT | ONEN_INT_PROG;
|
|
|
|
break;
|
|
|
|
case 0x1a: /* Program single/multiple spare area sector from buffer */
|
|
|
|
SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
|
|
|
|
|
|
|
|
SETBUF_S()
|
|
|
|
if (onenand_prog_spare(s, sec, s->count, buf))
|
|
|
|
s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG;
|
|
|
|
|
|
|
|
/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
|
|
|
|
* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
|
|
|
|
* then we need two split the read/write into two chunks.
|
|
|
|
*/
|
|
|
|
s->intstatus |= ONEN_INT | ONEN_INT_PROG;
|
|
|
|
break;
|
|
|
|
case 0x1b: /* Copy-back program */
|
|
|
|
SETBUF_S()
|
|
|
|
|
|
|
|
SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
|
|
|
|
if (onenand_load_main(s, sec, s->count, buf))
|
|
|
|
s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG;
|
|
|
|
|
|
|
|
SETADDR(ONEN_BUF_DEST_BLOCK, ONEN_BUF_DEST_PAGE)
|
|
|
|
if (onenand_prog_main(s, sec, s->count, buf))
|
|
|
|
s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG;
|
|
|
|
|
|
|
|
/* TODO: spare areas */
|
|
|
|
|
|
|
|
s->intstatus |= ONEN_INT | ONEN_INT_PROG;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 0x23: /* Unlock NAND array block(s) */
|
|
|
|
s->intstatus |= ONEN_INT;
|
|
|
|
|
|
|
|
/* XXX the previous (?) area should be locked automatically */
|
|
|
|
for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) {
|
|
|
|
if (b >= s->blocks) {
|
|
|
|
s->status |= ONEN_ERR_CMD;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
|
|
|
|
break;
|
|
|
|
|
|
|
|
s->wpstatus = s->blockwp[b] = ONEN_LOCK_UNLOCKED;
|
|
|
|
}
|
|
|
|
break;
|
2008-07-23 18:35:45 +02:00
|
|
|
case 0x27: /* Unlock All NAND array blocks */
|
|
|
|
s->intstatus |= ONEN_INT;
|
|
|
|
|
|
|
|
for (b = 0; b < s->blocks; b ++) {
|
|
|
|
if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
|
|
|
|
break;
|
|
|
|
|
|
|
|
s->wpstatus = s->blockwp[b] = ONEN_LOCK_UNLOCKED;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2008-04-14 23:57:44 +02:00
|
|
|
case 0x2a: /* Lock NAND array block(s) */
|
|
|
|
s->intstatus |= ONEN_INT;
|
|
|
|
|
|
|
|
for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) {
|
|
|
|
if (b >= s->blocks) {
|
|
|
|
s->status |= ONEN_ERR_CMD;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
|
|
|
|
break;
|
|
|
|
|
|
|
|
s->wpstatus = s->blockwp[b] = ONEN_LOCK_LOCKED;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 0x2c: /* Lock-tight NAND array block(s) */
|
|
|
|
s->intstatus |= ONEN_INT;
|
|
|
|
|
|
|
|
for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) {
|
|
|
|
if (b >= s->blocks) {
|
|
|
|
s->status |= ONEN_ERR_CMD;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (s->blockwp[b] == ONEN_LOCK_UNLOCKED)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
s->wpstatus = s->blockwp[b] = ONEN_LOCK_LOCKTIGHTEN;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 0x71: /* Erase-Verify-Read */
|
|
|
|
s->intstatus |= ONEN_INT;
|
|
|
|
break;
|
|
|
|
case 0x95: /* Multi-block erase */
|
|
|
|
qemu_irq_pulse(s->intr);
|
|
|
|
/* Fall through. */
|
|
|
|
case 0x94: /* Block erase */
|
|
|
|
sec = ((s->addr[ONEN_BUF_BLOCK] & 0xfff) |
|
|
|
|
(s->addr[ONEN_BUF_BLOCK] >> 15 ? s->density_mask : 0))
|
|
|
|
<< (BLOCK_SHIFT - 9);
|
|
|
|
if (onenand_erase(s, sec, 1 << (BLOCK_SHIFT - 9)))
|
|
|
|
s->status |= ONEN_ERR_CMD | ONEN_ERR_ERASE;
|
|
|
|
|
|
|
|
s->intstatus |= ONEN_INT | ONEN_INT_ERASE;
|
|
|
|
break;
|
|
|
|
case 0xb0: /* Erase suspend */
|
|
|
|
break;
|
|
|
|
case 0x30: /* Erase resume */
|
|
|
|
s->intstatus |= ONEN_INT | ONEN_INT_ERASE;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 0xf0: /* Reset NAND Flash core */
|
|
|
|
onenand_reset(s, 0);
|
|
|
|
break;
|
|
|
|
case 0xf3: /* Reset OneNAND */
|
|
|
|
onenand_reset(s, 0);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 0x65: /* OTP Access */
|
|
|
|
s->intstatus |= ONEN_INT;
|
2014-10-07 13:59:18 +02:00
|
|
|
s->blk_cur = NULL;
|
2008-04-14 23:57:44 +02:00
|
|
|
s->current = s->otp;
|
|
|
|
s->secs_cur = 1 << (BLOCK_SHIFT - 9);
|
|
|
|
s->addr[ONEN_BUF_BLOCK] = 0;
|
|
|
|
s->otpmode = 1;
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
s->status |= ONEN_ERR_CMD;
|
|
|
|
s->intstatus |= ONEN_INT;
|
|
|
|
fprintf(stderr, "%s: unknown OneNAND command %x\n",
|
2011-08-28 18:33:02 +02:00
|
|
|
__func__, s->command);
|
2008-04-14 23:57:44 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
onenand_intr_update(s);
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint64_t onenand_read(void *opaque, hwaddr addr,
|
2011-08-15 16:17:24 +02:00
|
|
|
unsigned size)
|
2008-04-14 23:57:44 +02:00
|
|
|
{
|
2009-05-10 02:44:56 +02:00
|
|
|
OneNANDState *s = (OneNANDState *) opaque;
|
2008-12-01 19:59:50 +01:00
|
|
|
int offset = addr >> s->shift;
|
2008-04-14 23:57:44 +02:00
|
|
|
|
|
|
|
switch (offset) {
|
2018-11-19 16:29:08 +01:00
|
|
|
case 0x0000 ... 0xbffe:
|
2008-12-01 19:59:50 +01:00
|
|
|
return lduw_le_p(s->boot[0] + addr);
|
2008-04-14 23:57:44 +02:00
|
|
|
|
|
|
|
case 0xf000: /* Manufacturer ID */
|
2011-07-29 17:35:26 +02:00
|
|
|
return s->id.man;
|
2008-04-14 23:57:44 +02:00
|
|
|
case 0xf001: /* Device ID */
|
2011-07-29 17:35:26 +02:00
|
|
|
return s->id.dev;
|
2008-04-14 23:57:44 +02:00
|
|
|
case 0xf002: /* Version ID */
|
2011-07-29 17:35:26 +02:00
|
|
|
return s->id.ver;
|
|
|
|
/* TODO: get the following values from a real chip! */
|
2008-04-14 23:57:44 +02:00
|
|
|
case 0xf003: /* Data Buffer size */
|
|
|
|
return 1 << PAGE_SHIFT;
|
|
|
|
case 0xf004: /* Boot Buffer size */
|
|
|
|
return 0x200;
|
|
|
|
case 0xf005: /* Amount of buffers */
|
|
|
|
return 1 | (2 << 8);
|
|
|
|
case 0xf006: /* Technology */
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
case 0xf100 ... 0xf107: /* Start addresses */
|
|
|
|
return s->addr[offset - 0xf100];
|
|
|
|
|
|
|
|
case 0xf200: /* Start buffer */
|
|
|
|
return (s->bufaddr << 8) | ((s->count - 1) & (1 << (PAGE_SHIFT - 10)));
|
|
|
|
|
|
|
|
case 0xf220: /* Command */
|
|
|
|
return s->command;
|
|
|
|
case 0xf221: /* System Configuration 1 */
|
|
|
|
return s->config[0] & 0xffe0;
|
|
|
|
case 0xf222: /* System Configuration 2 */
|
|
|
|
return s->config[1];
|
|
|
|
|
|
|
|
case 0xf240: /* Controller Status */
|
|
|
|
return s->status;
|
|
|
|
case 0xf241: /* Interrupt */
|
|
|
|
return s->intstatus;
|
|
|
|
case 0xf24c: /* Unlock Start Block Address */
|
|
|
|
return s->unladdr[0];
|
|
|
|
case 0xf24d: /* Unlock End Block Address */
|
|
|
|
return s->unladdr[1];
|
|
|
|
case 0xf24e: /* Write Protection Status */
|
|
|
|
return s->wpstatus;
|
|
|
|
|
|
|
|
case 0xff00: /* ECC Status */
|
|
|
|
return 0x00;
|
|
|
|
case 0xff01: /* ECC Result of main area data */
|
|
|
|
case 0xff02: /* ECC Result of spare area data */
|
|
|
|
case 0xff03: /* ECC Result of main area data */
|
|
|
|
case 0xff04: /* ECC Result of spare area data */
|
2017-11-08 23:56:34 +01:00
|
|
|
hw_error("%s: implement ECC\n", __func__);
|
2008-04-14 23:57:44 +02:00
|
|
|
return 0x0000;
|
|
|
|
}
|
|
|
|
|
|
|
|
fprintf(stderr, "%s: unknown OneNAND register %x\n",
|
2017-11-08 23:56:31 +01:00
|
|
|
__func__, offset);
|
2008-04-14 23:57:44 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void onenand_write(void *opaque, hwaddr addr,
|
2011-08-15 16:17:24 +02:00
|
|
|
uint64_t value, unsigned size)
|
2008-04-14 23:57:44 +02:00
|
|
|
{
|
2009-05-10 02:44:56 +02:00
|
|
|
OneNANDState *s = (OneNANDState *) opaque;
|
2008-12-01 19:59:50 +01:00
|
|
|
int offset = addr >> s->shift;
|
2008-04-14 23:57:44 +02:00
|
|
|
int sec;
|
|
|
|
|
|
|
|
switch (offset) {
|
|
|
|
case 0x0000 ... 0x01ff:
|
|
|
|
case 0x8000 ... 0x800f:
|
|
|
|
if (s->cycle) {
|
|
|
|
s->cycle = 0;
|
|
|
|
|
|
|
|
if (value == 0x0000) {
|
|
|
|
SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
|
|
|
|
onenand_load_main(s, sec,
|
|
|
|
1 << (PAGE_SHIFT - 9), s->data[0][0]);
|
|
|
|
s->addr[ONEN_BUF_PAGE] += 4;
|
|
|
|
s->addr[ONEN_BUF_PAGE] &= 0xff;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (value) {
|
|
|
|
case 0x00f0: /* Reset OneNAND */
|
|
|
|
onenand_reset(s, 0);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 0x00e0: /* Load Data into Buffer */
|
|
|
|
s->cycle = 1;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 0x0090: /* Read Identification Data */
|
|
|
|
memset(s->boot[0], 0, 3 << s->shift);
|
2011-07-29 17:35:26 +02:00
|
|
|
s->boot[0][0 << s->shift] = s->id.man & 0xff;
|
|
|
|
s->boot[0][1 << s->shift] = s->id.dev & 0xff;
|
2008-04-14 23:57:44 +02:00
|
|
|
s->boot[0][2 << s->shift] = s->wpstatus & 0xff;
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
2011-08-15 16:17:24 +02:00
|
|
|
fprintf(stderr, "%s: unknown OneNAND boot command %"PRIx64"\n",
|
2017-11-08 23:56:31 +01:00
|
|
|
__func__, value);
|
2008-04-14 23:57:44 +02:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 0xf100 ... 0xf107: /* Start addresses */
|
|
|
|
s->addr[offset - 0xf100] = value;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 0xf200: /* Start buffer */
|
|
|
|
s->bufaddr = (value >> 8) & 0xf;
|
|
|
|
if (PAGE_SHIFT == 11)
|
|
|
|
s->count = (value & 3) ?: 4;
|
|
|
|
else if (PAGE_SHIFT == 10)
|
|
|
|
s->count = (value & 1) ?: 2;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 0xf220: /* Command */
|
|
|
|
if (s->intstatus & (1 << 15))
|
|
|
|
break;
|
|
|
|
s->command = value;
|
2011-08-28 18:33:02 +02:00
|
|
|
onenand_command(s);
|
2008-04-14 23:57:44 +02:00
|
|
|
break;
|
|
|
|
case 0xf221: /* System Configuration 1 */
|
|
|
|
s->config[0] = value;
|
|
|
|
onenand_intr_update(s);
|
|
|
|
qemu_set_irq(s->rdy, (s->config[0] >> 7) & 1);
|
|
|
|
break;
|
|
|
|
case 0xf222: /* System Configuration 2 */
|
|
|
|
s->config[1] = value;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 0xf241: /* Interrupt */
|
|
|
|
s->intstatus &= value;
|
|
|
|
if ((1 << 15) & ~s->intstatus)
|
|
|
|
s->status &= ~(ONEN_ERR_CMD | ONEN_ERR_ERASE |
|
|
|
|
ONEN_ERR_PROG | ONEN_ERR_LOAD);
|
|
|
|
onenand_intr_update(s);
|
|
|
|
break;
|
|
|
|
case 0xf24c: /* Unlock Start Block Address */
|
|
|
|
s->unladdr[0] = value & (s->blocks - 1);
|
|
|
|
/* For some reason we have to set the end address to by default
|
|
|
|
* be same as start because the software forgets to write anything
|
|
|
|
* in there. */
|
|
|
|
s->unladdr[1] = value & (s->blocks - 1);
|
|
|
|
break;
|
|
|
|
case 0xf24d: /* Unlock End Block Address */
|
|
|
|
s->unladdr[1] = value & (s->blocks - 1);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
fprintf(stderr, "%s: unknown OneNAND register %x\n",
|
2017-11-08 23:56:31 +01:00
|
|
|
__func__, offset);
|
2008-04-14 23:57:44 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-08-15 16:17:24 +02:00
|
|
|
static const MemoryRegionOps onenand_ops = {
|
|
|
|
.read = onenand_read,
|
|
|
|
.write = onenand_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2008-04-14 23:57:44 +02:00
|
|
|
};
|
|
|
|
|
2013-07-24 10:44:48 +02:00
|
|
|
static int onenand_initfn(SysBusDevice *sbd)
|
2008-04-14 23:57:44 +02:00
|
|
|
{
|
2013-07-24 10:44:48 +02:00
|
|
|
DeviceState *dev = DEVICE(sbd);
|
|
|
|
OneNANDState *s = ONE_NAND(dev);
|
2011-08-28 18:22:17 +02:00
|
|
|
uint32_t size = 1 << (24 + ((s->id.dev >> 4) & 7));
|
2008-04-14 23:57:44 +02:00
|
|
|
void *ram;
|
2017-01-24 13:43:31 +01:00
|
|
|
Error *local_err = NULL;
|
2013-07-24 10:44:48 +02:00
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
s->base = (hwaddr)-1;
|
2009-09-21 20:11:34 +02:00
|
|
|
s->rdy = NULL;
|
2008-04-14 23:57:44 +02:00
|
|
|
s->blocks = size >> BLOCK_SHIFT;
|
|
|
|
s->secs = size >> 9;
|
2011-08-21 05:09:37 +02:00
|
|
|
s->blockwp = g_malloc(s->blocks);
|
2011-08-28 18:22:17 +02:00
|
|
|
s->density_mask = (s->id.dev & 0x08)
|
|
|
|
? (1 << (6 + ((s->id.dev >> 4) & 7))) : 0;
|
2013-06-07 03:25:08 +02:00
|
|
|
memory_region_init_io(&s->iomem, OBJECT(s), &onenand_ops, s, "onenand",
|
2011-08-15 16:17:24 +02:00
|
|
|
0x10000 << s->shift);
|
2014-10-07 13:59:18 +02:00
|
|
|
if (!s->blk) {
|
2011-08-21 05:09:37 +02:00
|
|
|
s->image = memset(g_malloc(size + (size >> 5)),
|
2011-08-28 18:22:17 +02:00
|
|
|
0xff, size + (size >> 5));
|
|
|
|
} else {
|
2014-10-07 13:59:18 +02:00
|
|
|
if (blk_is_read_only(s->blk)) {
|
2011-10-20 14:53:35 +02:00
|
|
|
error_report("Can't use a read-only drive");
|
|
|
|
return -1;
|
|
|
|
}
|
2017-01-24 13:43:31 +01:00
|
|
|
blk_set_perm(s->blk, BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE,
|
|
|
|
BLK_PERM_ALL, &local_err);
|
|
|
|
if (local_err) {
|
|
|
|
error_report_err(local_err);
|
|
|
|
return -1;
|
|
|
|
}
|
2014-10-07 13:59:18 +02:00
|
|
|
s->blk_cur = s->blk;
|
2011-07-30 06:53:39 +02:00
|
|
|
}
|
2011-08-21 05:09:37 +02:00
|
|
|
s->otp = memset(g_malloc((64 + 2) << PAGE_SHIFT),
|
2008-04-14 23:57:44 +02:00
|
|
|
0xff, (64 + 2) << PAGE_SHIFT);
|
2017-07-07 16:42:49 +02:00
|
|
|
memory_region_init_ram_nomigrate(&s->ram, OBJECT(s), "onenand.ram",
|
Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
|
err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 16:51:43 +02:00
|
|
|
0xc000 << s->shift, &error_fatal);
|
2011-12-20 14:59:12 +01:00
|
|
|
vmstate_register_ram_global(&s->ram);
|
2011-08-15 16:17:24 +02:00
|
|
|
ram = memory_region_get_ram_ptr(&s->ram);
|
2008-04-14 23:57:44 +02:00
|
|
|
s->boot[0] = ram + (0x0000 << s->shift);
|
|
|
|
s->boot[1] = ram + (0x8000 << s->shift);
|
|
|
|
s->data[0][0] = ram + ((0x0200 + (0 << (PAGE_SHIFT - 1))) << s->shift);
|
|
|
|
s->data[0][1] = ram + ((0x8010 + (0 << (PAGE_SHIFT - 6))) << s->shift);
|
|
|
|
s->data[1][0] = ram + ((0x0200 + (1 << (PAGE_SHIFT - 1))) << s->shift);
|
|
|
|
s->data[1][1] = ram + ((0x8010 + (1 << (PAGE_SHIFT - 6))) << s->shift);
|
2011-08-15 16:17:24 +02:00
|
|
|
onenand_mem_setup(s);
|
2013-07-24 10:44:48 +02:00
|
|
|
sysbus_init_irq(sbd, &s->intr);
|
|
|
|
sysbus_init_mmio(sbd, &s->container);
|
|
|
|
vmstate_register(dev,
|
2011-08-28 18:22:17 +02:00
|
|
|
((s->shift & 0x7f) << 24)
|
|
|
|
| ((s->id.man & 0xff) << 16)
|
|
|
|
| ((s->id.dev & 0xff) << 8)
|
|
|
|
| (s->id.ver & 0xff),
|
|
|
|
&vmstate_onenand, s);
|
|
|
|
return 0;
|
|
|
|
}
|
2008-04-14 23:57:44 +02:00
|
|
|
|
2012-01-24 20:12:29 +01:00
|
|
|
static Property onenand_properties[] = {
|
|
|
|
DEFINE_PROP_UINT16("manufacturer_id", OneNANDState, id.man, 0),
|
|
|
|
DEFINE_PROP_UINT16("device_id", OneNANDState, id.dev, 0),
|
|
|
|
DEFINE_PROP_UINT16("version_id", OneNANDState, id.ver, 0),
|
|
|
|
DEFINE_PROP_INT32("shift", OneNANDState, shift, 0),
|
2014-10-07 13:59:18 +02:00
|
|
|
DEFINE_PROP_DRIVE("drive", OneNANDState, blk),
|
2012-01-24 20:12:29 +01:00
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
|
|
|
static void onenand_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 04:34:16 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2012-01-24 20:12:29 +01:00
|
|
|
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
|
|
|
|
|
|
|
k->init = onenand_initfn;
|
2011-12-08 04:34:16 +01:00
|
|
|
dc->reset = onenand_system_reset;
|
|
|
|
dc->props = onenand_properties;
|
2012-01-24 20:12:29 +01:00
|
|
|
}
|
|
|
|
|
2013-01-10 16:19:07 +01:00
|
|
|
static const TypeInfo onenand_info = {
|
2013-07-24 10:44:48 +02:00
|
|
|
.name = TYPE_ONE_NAND,
|
2011-12-08 04:34:16 +01:00
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(OneNANDState),
|
|
|
|
.class_init = onenand_class_init,
|
2011-08-28 18:22:17 +02:00
|
|
|
};
|
2008-04-14 23:57:44 +02:00
|
|
|
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2012-02-09 15:20:55 +01:00
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static void onenand_register_types(void)
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2011-08-28 18:22:17 +02:00
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{
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2011-12-08 04:34:16 +01:00
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type_register_static(&onenand_info);
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2008-04-14 23:57:44 +02:00
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}
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2008-07-29 16:19:16 +02:00
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2011-08-28 18:22:17 +02:00
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void *onenand_raw_otp(DeviceState *onenand_device)
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2008-07-29 16:19:16 +02:00
|
|
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{
|
2013-07-24 10:44:48 +02:00
|
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OneNANDState *s = ONE_NAND(onenand_device);
|
|
|
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return s->otp;
|
2008-07-29 16:19:16 +02:00
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}
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2011-08-28 18:22:17 +02:00
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2012-02-09 15:20:55 +01:00
|
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type_init(onenand_register_types)
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