2011-10-30 18:16:46 +01:00
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/*
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* QEMU SPAPR PCI BUS definitions
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*
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* Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#if !defined(__HW_SPAPR_H__)
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#error Please include spapr.h before this file!
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#endif
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#if !defined(__HW_SPAPR_PCI_H__)
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#define __HW_SPAPR_PCI_H__
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2012-12-12 13:24:50 +01:00
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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2011-10-30 18:16:46 +01:00
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#include "hw/xics.h"
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2012-08-07 18:10:37 +02:00
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#define SPAPR_MSIX_MAX_DEVS 32
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2012-08-20 19:08:05 +02:00
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#define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge"
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#define SPAPR_PCI_HOST_BRIDGE(obj) \
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OBJECT_CHECK(sPAPRPHBState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE)
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2011-10-30 18:16:46 +01:00
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typedef struct sPAPRPHBState {
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2012-08-20 19:08:09 +02:00
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PCIHostState parent_obj;
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2011-10-30 18:16:46 +01:00
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2013-01-23 18:20:39 +01:00
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int32_t index;
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2011-10-30 18:16:46 +01:00
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uint64_t buid;
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2012-03-12 18:50:24 +01:00
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char *dtbusname;
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2011-10-30 18:16:46 +01:00
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MemoryRegion memspace, iospace;
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2012-10-23 12:30:10 +02:00
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hwaddr mem_win_addr, mem_win_size, io_win_addr, io_win_size;
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hwaddr msi_win_addr;
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2012-10-29 18:24:57 +01:00
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MemoryRegion memwindow, iowindow, msiwindow;
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2012-08-07 18:10:37 +02:00
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2012-08-07 18:10:38 +02:00
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uint32_t dma_liobn;
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uint64_t dma_window_start;
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uint64_t dma_window_size;
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2012-06-27 06:50:46 +02:00
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DMAContext *dma;
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2011-10-30 18:16:46 +01:00
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struct {
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2012-08-07 18:10:32 +02:00
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uint32_t irq;
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2012-04-25 19:55:42 +02:00
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} lsi_table[PCI_NUM_PINS];
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2011-10-30 18:16:46 +01:00
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2012-08-07 18:10:37 +02:00
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struct {
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uint32_t config_addr;
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uint32_t irq;
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int nvec;
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} msi_table[SPAPR_MSIX_MAX_DEVS];
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2011-10-30 18:16:46 +01:00
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QLIST_ENTRY(sPAPRPHBState) list;
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} sPAPRPHBState;
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2013-01-23 18:20:39 +01:00
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#define SPAPR_PCI_BASE_BUID 0x800000020000000ULL
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#define SPAPR_PCI_WINDOW_BASE 0x10000000000ULL
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#define SPAPR_PCI_WINDOW_SPACING 0x1000000000ULL
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#define SPAPR_PCI_MMIO_WIN_OFF 0xA0000000
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#define SPAPR_PCI_MMIO_WIN_SIZE 0x20000000
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#define SPAPR_PCI_IO_WIN_OFF 0x80000000
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#define SPAPR_PCI_IO_WIN_SIZE 0x10000
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#define SPAPR_PCI_MSI_WIN_OFF 0x90000000
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#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
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2012-08-07 18:10:32 +02:00
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static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
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{
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return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq);
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}
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2013-03-13 16:53:25 +01:00
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PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index);
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2011-10-30 18:16:46 +01:00
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2012-06-13 20:40:06 +02:00
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int spapr_populate_pci_dt(sPAPRPHBState *phb,
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uint32_t xics_phandle,
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void *fdt);
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2011-10-30 18:16:46 +01:00
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2012-08-07 18:10:33 +02:00
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void spapr_pci_rtas_init(void);
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2011-10-30 18:16:46 +01:00
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#endif /* __HW_SPAPR_PCI_H__ */
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