2012-07-04 12:43:33 +02:00
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/*
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2013-06-03 18:17:45 +02:00
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* IMX GPT Timer
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2012-07-04 12:43:33 +02:00
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*
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* Copyright (c) 2008 OK Labs
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* Copyright (c) 2011 NICTA Pty Ltd
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2012-08-10 22:03:26 +02:00
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* Originally written by Hans Jiang
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2012-07-04 12:43:33 +02:00
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* Updated by Peter Chubb
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2013-06-25 19:34:13 +02:00
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* Updated by Jean-Christophe Dubois
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2012-07-04 12:43:33 +02:00
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*
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2012-08-10 22:03:26 +02:00
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* This code is licensed under GPL version 2 or later. See
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2012-07-04 12:43:33 +02:00
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* the COPYING file in the top-level directory.
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*
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*/
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2013-02-04 15:40:22 +01:00
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#include "hw/hw.h"
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2013-06-03 18:17:45 +02:00
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#include "qemu/bitops.h"
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2012-12-17 18:20:00 +01:00
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#include "qemu/timer.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/ptimer.h"
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#include "hw/sysbus.h"
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2013-02-05 17:06:20 +01:00
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#include "hw/arm/imx.h"
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2012-07-04 12:43:33 +02:00
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2013-06-25 19:34:13 +02:00
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#define TYPE_IMX_GPT "imx.gpt"
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/*
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* Define to 1 for debug messages
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*/
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#define DEBUG_TIMER 0
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#if DEBUG_TIMER
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2013-06-25 19:34:13 +02:00
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static char const *imx_gpt_reg_name(uint32_t reg)
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2013-06-25 19:34:13 +02:00
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{
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switch (reg) {
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case 0:
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return "CR";
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case 1:
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return "PR";
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case 2:
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return "SR";
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case 3:
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return "IR";
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case 4:
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return "OCR1";
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case 5:
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return "OCR2";
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case 6:
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return "OCR3";
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case 7:
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return "ICR1";
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case 8:
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return "ICR2";
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case 9:
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return "CNT";
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default:
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return "[?]";
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}
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}
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2012-07-04 12:43:33 +02:00
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# define DPRINTF(fmt, args...) \
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2013-06-25 19:34:13 +02:00
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do { printf("%s: " fmt , __func__, ##args); } while (0)
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2012-07-04 12:43:33 +02:00
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#else
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# define DPRINTF(fmt, args...) do {} while (0)
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#endif
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/*
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* Define to 1 for messages about attempts to
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* access unimplemented registers or similar.
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*/
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#define DEBUG_IMPLEMENTATION 1
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#if DEBUG_IMPLEMENTATION
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2013-06-25 19:34:13 +02:00
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# define IPRINTF(fmt, args...) \
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2013-06-25 19:34:13 +02:00
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do { fprintf(stderr, "%s: " fmt, __func__, ##args); } while (0)
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2012-07-04 12:43:33 +02:00
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#else
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# define IPRINTF(fmt, args...) do {} while (0)
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#endif
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2013-06-25 19:34:13 +02:00
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#define IMX_GPT(obj) \
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OBJECT_CHECK(IMXGPTState, (obj), TYPE_IMX_GPT)
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2012-07-04 12:43:33 +02:00
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/*
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* GPT : General purpose timer
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*
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* This timer counts up continuously while it is enabled, resetting itself
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* to 0 when it reaches TIMER_MAX (in freerun mode) or when it
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2013-06-25 19:34:13 +02:00
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* reaches the value of one of the ocrX (in periodic mode).
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2012-07-04 12:43:33 +02:00
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*/
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#define TIMER_MAX 0XFFFFFFFFUL
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/* Control register. Not all of these bits have any effect (yet) */
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#define GPT_CR_EN (1 << 0) /* GPT Enable */
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#define GPT_CR_ENMOD (1 << 1) /* GPT Enable Mode */
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#define GPT_CR_DBGEN (1 << 2) /* GPT Debug mode enable */
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#define GPT_CR_WAITEN (1 << 3) /* GPT Wait Mode Enable */
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#define GPT_CR_DOZEN (1 << 4) /* GPT Doze mode enable */
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#define GPT_CR_STOPEN (1 << 5) /* GPT Stop Mode Enable */
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#define GPT_CR_CLKSRC_SHIFT (6)
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#define GPT_CR_CLKSRC_MASK (0x7)
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#define GPT_CR_FRR (1 << 9) /* Freerun or Restart */
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#define GPT_CR_SWR (1 << 15) /* Software Reset */
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#define GPT_CR_IM1 (3 << 16) /* Input capture channel 1 mode (2 bits) */
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#define GPT_CR_IM2 (3 << 18) /* Input capture channel 2 mode (2 bits) */
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#define GPT_CR_OM1 (7 << 20) /* Output Compare Channel 1 Mode (3 bits) */
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#define GPT_CR_OM2 (7 << 23) /* Output Compare Channel 2 Mode (3 bits) */
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#define GPT_CR_OM3 (7 << 26) /* Output Compare Channel 3 Mode (3 bits) */
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#define GPT_CR_FO1 (1 << 29) /* Force Output Compare Channel 1 */
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#define GPT_CR_FO2 (1 << 30) /* Force Output Compare Channel 2 */
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#define GPT_CR_FO3 (1 << 31) /* Force Output Compare Channel 3 */
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#define GPT_SR_OF1 (1 << 0)
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2013-06-25 19:34:13 +02:00
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#define GPT_SR_OF2 (1 << 1)
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#define GPT_SR_OF3 (1 << 2)
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2012-07-04 12:43:33 +02:00
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#define GPT_SR_ROV (1 << 5)
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#define GPT_IR_OF1IE (1 << 0)
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2013-06-25 19:34:13 +02:00
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#define GPT_IR_OF2IE (1 << 1)
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#define GPT_IR_OF3IE (1 << 2)
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2012-07-04 12:43:33 +02:00
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#define GPT_IR_ROVIE (1 << 5)
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typedef struct {
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SysBusDevice busdev;
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ptimer_state *timer;
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MemoryRegion iomem;
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DeviceState *ccm;
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uint32_t cr;
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uint32_t pr;
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uint32_t sr;
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uint32_t ir;
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uint32_t ocr1;
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2013-05-03 19:21:02 +02:00
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uint32_t ocr2;
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uint32_t ocr3;
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uint32_t icr1;
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uint32_t icr2;
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2012-07-04 12:43:33 +02:00
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uint32_t cnt;
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2013-06-25 19:34:13 +02:00
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uint32_t next_timeout;
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uint32_t next_int;
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uint32_t freq;
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2012-07-04 12:43:33 +02:00
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qemu_irq irq;
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2013-06-25 19:34:13 +02:00
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} IMXGPTState;
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2012-07-04 12:43:33 +02:00
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2013-06-25 19:34:13 +02:00
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static const VMStateDescription vmstate_imx_timer_gpt = {
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2013-06-27 13:03:44 +02:00
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.name = "imx.gpt",
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2013-06-25 19:34:13 +02:00
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.version_id = 3,
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.minimum_version_id = 3,
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.minimum_version_id_old = 3,
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2012-07-04 12:43:33 +02:00
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.fields = (VMStateField[]) {
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2013-06-25 19:34:13 +02:00
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VMSTATE_UINT32(cr, IMXGPTState),
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VMSTATE_UINT32(pr, IMXGPTState),
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VMSTATE_UINT32(sr, IMXGPTState),
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VMSTATE_UINT32(ir, IMXGPTState),
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VMSTATE_UINT32(ocr1, IMXGPTState),
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VMSTATE_UINT32(ocr2, IMXGPTState),
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VMSTATE_UINT32(ocr3, IMXGPTState),
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VMSTATE_UINT32(icr1, IMXGPTState),
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VMSTATE_UINT32(icr2, IMXGPTState),
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VMSTATE_UINT32(cnt, IMXGPTState),
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VMSTATE_UINT32(next_timeout, IMXGPTState),
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VMSTATE_UINT32(next_int, IMXGPTState),
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VMSTATE_UINT32(freq, IMXGPTState),
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VMSTATE_PTIMER(timer, IMXGPTState),
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2012-07-04 12:43:33 +02:00
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VMSTATE_END_OF_LIST()
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}
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};
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2013-06-25 19:34:13 +02:00
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static const IMXClk imx_gpt_clocks[] = {
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2012-07-04 12:43:33 +02:00
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NOCLK, /* 000 No clock source */
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IPG, /* 001 ipg_clk, 532MHz*/
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IPG, /* 010 ipg_clk_highfreq */
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NOCLK, /* 011 not defined */
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CLK_32k, /* 100 ipg_clk_32k */
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NOCLK, /* 101 not defined */
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NOCLK, /* 110 not defined */
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NOCLK, /* 111 not defined */
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};
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2013-06-25 19:34:13 +02:00
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static void imx_gpt_set_freq(IMXGPTState *s)
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2012-07-04 12:43:33 +02:00
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{
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2013-06-25 19:34:13 +02:00
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uint32_t clksrc = extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3);
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2013-06-25 19:34:13 +02:00
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uint32_t freq = imx_clock_frequency(s->ccm, imx_gpt_clocks[clksrc])
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2013-06-25 19:34:13 +02:00
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/ (1 + s->pr);
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s->freq = freq;
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2012-07-04 12:43:33 +02:00
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2013-06-25 19:34:13 +02:00
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DPRINTF("Setting clksrc %d to frequency %d\n", clksrc, freq);
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2013-06-03 18:17:45 +02:00
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2012-07-04 12:43:33 +02:00
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if (freq) {
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ptimer_set_freq(s->timer, freq);
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}
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}
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2013-06-25 19:34:13 +02:00
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static void imx_gpt_update_int(IMXGPTState *s)
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2012-07-04 12:43:33 +02:00
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{
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2013-06-25 19:34:13 +02:00
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if ((s->sr & s->ir) && (s->cr & GPT_CR_EN)) {
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qemu_irq_raise(s->irq);
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} else {
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qemu_irq_lower(s->irq);
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}
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2012-07-04 12:43:33 +02:00
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}
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2013-06-25 19:34:13 +02:00
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static uint32_t imx_gpt_update_count(IMXGPTState *s)
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2012-07-04 12:43:33 +02:00
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{
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2013-06-25 19:34:13 +02:00
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s->cnt = s->next_timeout - (uint32_t)ptimer_get_count(s->timer);
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2012-07-04 12:43:33 +02:00
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return s->cnt;
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}
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2013-06-25 19:34:13 +02:00
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static inline uint32_t imx_gpt_find_limit(uint32_t count, uint32_t reg,
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2013-06-25 19:34:13 +02:00
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uint32_t timeout)
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2012-07-04 12:43:33 +02:00
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{
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2013-06-25 19:34:13 +02:00
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if ((count < reg) && (timeout > reg)) {
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timeout = reg;
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}
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return timeout;
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}
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2012-07-04 12:43:33 +02:00
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2013-06-25 19:34:13 +02:00
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static void imx_gpt_compute_next_timeout(IMXGPTState *s, bool event)
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2013-06-25 19:34:13 +02:00
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{
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uint32_t timeout = TIMER_MAX;
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uint32_t count = 0;
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long long limit;
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if (!(s->cr & GPT_CR_EN)) {
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/* if not enabled just return */
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2012-07-04 12:43:33 +02:00
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return;
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}
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2013-06-25 19:34:13 +02:00
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if (event) {
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/* This is a timer event */
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if ((s->cr & GPT_CR_FRR) && (s->next_timeout != TIMER_MAX)) {
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/*
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* if we are in free running mode and we have not reached
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* the TIMER_MAX limit, then update the count
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*/
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2013-06-25 19:34:13 +02:00
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count = imx_gpt_update_count(s);
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2013-06-25 19:34:13 +02:00
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}
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2012-07-04 12:43:33 +02:00
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} else {
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2013-06-25 19:34:13 +02:00
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/* not a timer event, then just update the count */
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2013-06-25 19:34:13 +02:00
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count = imx_gpt_update_count(s);
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2013-06-25 19:34:13 +02:00
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}
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/* now, find the next timeout related to count */
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if (s->ir & GPT_IR_OF1IE) {
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2013-06-25 19:34:13 +02:00
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timeout = imx_gpt_find_limit(count, s->ocr1, timeout);
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2013-06-25 19:34:13 +02:00
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}
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if (s->ir & GPT_IR_OF2IE) {
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2013-06-25 19:34:13 +02:00
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timeout = imx_gpt_find_limit(count, s->ocr2, timeout);
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2013-06-25 19:34:13 +02:00
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}
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if (s->ir & GPT_IR_OF3IE) {
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2013-06-25 19:34:13 +02:00
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timeout = imx_gpt_find_limit(count, s->ocr3, timeout);
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2013-06-25 19:34:13 +02:00
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}
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/* find the next set of interrupts to raise for next timer event */
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s->next_int = 0;
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if ((s->ir & GPT_IR_OF1IE) && (timeout == s->ocr1)) {
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s->next_int |= GPT_SR_OF1;
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}
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if ((s->ir & GPT_IR_OF2IE) && (timeout == s->ocr2)) {
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s->next_int |= GPT_SR_OF2;
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}
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if ((s->ir & GPT_IR_OF3IE) && (timeout == s->ocr3)) {
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s->next_int |= GPT_SR_OF3;
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}
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if ((s->ir & GPT_IR_ROVIE) && (timeout == TIMER_MAX)) {
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s->next_int |= GPT_SR_ROV;
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}
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/* the new range to count down from */
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2013-06-25 19:34:13 +02:00
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limit = timeout - imx_gpt_update_count(s);
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2013-06-25 19:34:13 +02:00
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if (limit < 0) {
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/*
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* if we reach here, then QEMU is running too slow and we pass the
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* timeout limit while computing it. Let's deliver the interrupt
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* and compute a new limit.
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*/
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s->sr |= s->next_int;
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2013-06-25 19:34:13 +02:00
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imx_gpt_compute_next_timeout(s, event);
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2013-06-25 19:34:13 +02:00
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2013-06-25 19:34:13 +02:00
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imx_gpt_update_int(s);
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2013-06-25 19:34:13 +02:00
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} else {
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/* New timeout value */
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s->next_timeout = timeout;
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/* reset the limit to the computed range */
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ptimer_set_limit(s->timer, limit, 1);
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2012-07-04 12:43:33 +02:00
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}
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}
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2013-06-25 19:34:13 +02:00
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static uint64_t imx_gpt_read(void *opaque, hwaddr offset, unsigned size)
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2012-07-04 12:43:33 +02:00
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{
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2013-06-25 19:34:13 +02:00
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IMXGPTState *s = IMX_GPT(opaque);
|
2013-06-25 19:34:13 +02:00
|
|
|
uint32_t reg_value = 0;
|
|
|
|
uint32_t reg = offset >> 2;
|
2012-07-04 12:43:33 +02:00
|
|
|
|
2013-06-25 19:34:13 +02:00
|
|
|
switch (reg) {
|
2012-07-04 12:43:33 +02:00
|
|
|
case 0: /* Control Register */
|
2013-06-25 19:34:13 +02:00
|
|
|
reg_value = s->cr;
|
|
|
|
break;
|
2012-07-04 12:43:33 +02:00
|
|
|
|
|
|
|
case 1: /* prescaler */
|
2013-06-25 19:34:13 +02:00
|
|
|
reg_value = s->pr;
|
|
|
|
break;
|
2012-07-04 12:43:33 +02:00
|
|
|
|
|
|
|
case 2: /* Status Register */
|
2013-06-25 19:34:13 +02:00
|
|
|
reg_value = s->sr;
|
|
|
|
break;
|
2012-07-04 12:43:33 +02:00
|
|
|
|
|
|
|
case 3: /* Interrupt Register */
|
2013-06-25 19:34:13 +02:00
|
|
|
reg_value = s->ir;
|
|
|
|
break;
|
2012-07-04 12:43:33 +02:00
|
|
|
|
|
|
|
case 4: /* Output Compare Register 1 */
|
2013-06-25 19:34:13 +02:00
|
|
|
reg_value = s->ocr1;
|
|
|
|
break;
|
2012-07-04 12:43:33 +02:00
|
|
|
|
2013-05-03 19:21:02 +02:00
|
|
|
case 5: /* Output Compare Register 2 */
|
2013-06-25 19:34:13 +02:00
|
|
|
reg_value = s->ocr2;
|
|
|
|
break;
|
2013-05-03 19:21:02 +02:00
|
|
|
|
|
|
|
case 6: /* Output Compare Register 3 */
|
2013-06-25 19:34:13 +02:00
|
|
|
reg_value = s->ocr3;
|
|
|
|
break;
|
2013-05-03 19:21:02 +02:00
|
|
|
|
|
|
|
case 7: /* input Capture Register 1 */
|
2013-06-25 19:34:13 +02:00
|
|
|
qemu_log_mask(LOG_UNIMP, "icr1 feature is not implemented\n");
|
|
|
|
reg_value = s->icr1;
|
|
|
|
break;
|
2013-05-03 19:21:02 +02:00
|
|
|
|
|
|
|
case 8: /* input Capture Register 2 */
|
2013-06-25 19:34:13 +02:00
|
|
|
qemu_log_mask(LOG_UNIMP, "icr2 feature is not implemented\n");
|
|
|
|
reg_value = s->icr2;
|
|
|
|
break;
|
2012-07-04 12:43:33 +02:00
|
|
|
|
|
|
|
case 9: /* cnt */
|
2013-06-25 19:34:13 +02:00
|
|
|
imx_gpt_update_count(s);
|
2013-06-25 19:34:13 +02:00
|
|
|
reg_value = s->cnt;
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
IPRINTF("Bad offset %x\n", reg);
|
|
|
|
break;
|
2012-07-04 12:43:33 +02:00
|
|
|
}
|
|
|
|
|
2013-06-25 19:34:13 +02:00
|
|
|
DPRINTF("(%s) = 0x%08x\n", imx_gpt_reg_name(reg), reg_value);
|
2013-05-03 19:21:02 +02:00
|
|
|
|
2013-06-25 19:34:13 +02:00
|
|
|
return reg_value;
|
2012-07-04 12:43:33 +02:00
|
|
|
}
|
|
|
|
|
2013-06-25 19:34:13 +02:00
|
|
|
static void imx_gpt_reset(DeviceState *dev)
|
2012-07-04 12:43:33 +02:00
|
|
|
{
|
2013-06-25 19:34:13 +02:00
|
|
|
IMXGPTState *s = IMX_GPT(dev);
|
2012-07-04 12:43:33 +02:00
|
|
|
|
2013-06-25 19:34:13 +02:00
|
|
|
/* stop timer */
|
|
|
|
ptimer_stop(s->timer);
|
|
|
|
|
2012-07-04 12:43:33 +02:00
|
|
|
/*
|
|
|
|
* Soft reset doesn't touch some bits; hard reset clears them
|
|
|
|
*/
|
2013-05-03 19:21:02 +02:00
|
|
|
s->cr &= ~(GPT_CR_EN|GPT_CR_ENMOD|GPT_CR_STOPEN|GPT_CR_DOZEN|
|
|
|
|
GPT_CR_WAITEN|GPT_CR_DBGEN);
|
2012-07-04 12:43:33 +02:00
|
|
|
s->sr = 0;
|
|
|
|
s->pr = 0;
|
|
|
|
s->ir = 0;
|
|
|
|
s->cnt = 0;
|
|
|
|
s->ocr1 = TIMER_MAX;
|
2013-05-03 19:21:02 +02:00
|
|
|
s->ocr2 = TIMER_MAX;
|
|
|
|
s->ocr3 = TIMER_MAX;
|
|
|
|
s->icr1 = 0;
|
|
|
|
s->icr2 = 0;
|
2013-06-25 19:34:13 +02:00
|
|
|
|
|
|
|
s->next_timeout = TIMER_MAX;
|
|
|
|
s->next_int = 0;
|
|
|
|
|
|
|
|
/* compute new freq */
|
2013-06-25 19:34:13 +02:00
|
|
|
imx_gpt_set_freq(s);
|
2013-06-25 19:34:13 +02:00
|
|
|
|
|
|
|
/* reset the limit to TIMER_MAX */
|
|
|
|
ptimer_set_limit(s->timer, TIMER_MAX, 1);
|
|
|
|
|
|
|
|
/* if the timer is still enabled, restart it */
|
|
|
|
if (s->freq && (s->cr & GPT_CR_EN)) {
|
|
|
|
ptimer_run(s->timer, 1);
|
|
|
|
}
|
2012-07-04 12:43:33 +02:00
|
|
|
}
|
|
|
|
|
2013-06-25 19:34:13 +02:00
|
|
|
static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value,
|
|
|
|
unsigned size)
|
2012-07-04 12:43:33 +02:00
|
|
|
{
|
2013-06-25 19:34:13 +02:00
|
|
|
IMXGPTState *s = IMX_GPT(opaque);
|
2013-06-25 19:34:13 +02:00
|
|
|
uint32_t oldreg;
|
|
|
|
uint32_t reg = offset >> 2;
|
|
|
|
|
2013-06-25 19:34:13 +02:00
|
|
|
DPRINTF("(%s, value = 0x%08x)\n", imx_gpt_reg_name(reg),
|
2013-06-25 19:34:13 +02:00
|
|
|
(uint32_t)value);
|
|
|
|
|
|
|
|
switch (reg) {
|
|
|
|
case 0:
|
|
|
|
oldreg = s->cr;
|
|
|
|
s->cr = value & ~0x7c14;
|
|
|
|
if (s->cr & GPT_CR_SWR) { /* force reset */
|
|
|
|
/* handle the reset */
|
2013-06-25 19:34:13 +02:00
|
|
|
imx_gpt_reset(DEVICE(s));
|
2013-06-25 19:34:13 +02:00
|
|
|
} else {
|
|
|
|
/* set our freq, as the source might have changed */
|
2013-06-25 19:34:13 +02:00
|
|
|
imx_gpt_set_freq(s);
|
2013-06-25 19:34:13 +02:00
|
|
|
|
|
|
|
if ((oldreg ^ s->cr) & GPT_CR_EN) {
|
|
|
|
if (s->cr & GPT_CR_EN) {
|
|
|
|
if (s->cr & GPT_CR_ENMOD) {
|
|
|
|
s->next_timeout = TIMER_MAX;
|
|
|
|
ptimer_set_count(s->timer, TIMER_MAX);
|
2013-06-25 19:34:13 +02:00
|
|
|
imx_gpt_compute_next_timeout(s, false);
|
2013-06-25 19:34:13 +02:00
|
|
|
}
|
|
|
|
ptimer_run(s->timer, 1);
|
|
|
|
} else {
|
|
|
|
/* stop timer */
|
|
|
|
ptimer_stop(s->timer);
|
2012-07-04 12:43:33 +02:00
|
|
|
}
|
2013-06-25 19:34:13 +02:00
|
|
|
}
|
2012-07-04 12:43:33 +02:00
|
|
|
}
|
2013-06-25 19:34:13 +02:00
|
|
|
break;
|
2012-07-04 12:43:33 +02:00
|
|
|
|
|
|
|
case 1: /* Prescaler */
|
|
|
|
s->pr = value & 0xfff;
|
2013-06-25 19:34:13 +02:00
|
|
|
imx_gpt_set_freq(s);
|
2013-06-25 19:34:13 +02:00
|
|
|
break;
|
2012-07-04 12:43:33 +02:00
|
|
|
|
|
|
|
case 2: /* SR */
|
2013-06-25 19:34:13 +02:00
|
|
|
s->sr &= ~(value & 0x3f);
|
2013-06-25 19:34:13 +02:00
|
|
|
imx_gpt_update_int(s);
|
2013-06-25 19:34:13 +02:00
|
|
|
break;
|
2012-07-04 12:43:33 +02:00
|
|
|
|
|
|
|
case 3: /* IR -- interrupt register */
|
|
|
|
s->ir = value & 0x3f;
|
2013-06-25 19:34:13 +02:00
|
|
|
imx_gpt_update_int(s);
|
2013-06-25 19:34:13 +02:00
|
|
|
|
2013-06-25 19:34:13 +02:00
|
|
|
imx_gpt_compute_next_timeout(s, false);
|
2013-06-25 19:34:13 +02:00
|
|
|
|
|
|
|
break;
|
2012-07-04 12:43:33 +02:00
|
|
|
|
|
|
|
case 4: /* OCR1 -- output compare register */
|
2013-06-25 19:34:13 +02:00
|
|
|
s->ocr1 = value;
|
|
|
|
|
2012-07-04 12:43:33 +02:00
|
|
|
/* In non-freerun mode, reset count when this register is written */
|
|
|
|
if (!(s->cr & GPT_CR_FRR)) {
|
2013-06-25 19:34:13 +02:00
|
|
|
s->next_timeout = TIMER_MAX;
|
|
|
|
ptimer_set_limit(s->timer, TIMER_MAX, 1);
|
2012-07-04 12:43:33 +02:00
|
|
|
}
|
2013-06-25 19:34:13 +02:00
|
|
|
|
|
|
|
/* compute the new timeout */
|
2013-06-25 19:34:13 +02:00
|
|
|
imx_gpt_compute_next_timeout(s, false);
|
2013-06-25 19:34:13 +02:00
|
|
|
|
|
|
|
break;
|
2012-07-04 12:43:33 +02:00
|
|
|
|
2013-05-03 19:21:02 +02:00
|
|
|
case 5: /* OCR2 -- output compare register */
|
2013-06-25 19:34:13 +02:00
|
|
|
s->ocr2 = value;
|
|
|
|
|
|
|
|
/* compute the new timeout */
|
2013-06-25 19:34:13 +02:00
|
|
|
imx_gpt_compute_next_timeout(s, false);
|
2013-06-25 19:34:13 +02:00
|
|
|
|
|
|
|
break;
|
|
|
|
|
2013-05-03 19:21:02 +02:00
|
|
|
case 6: /* OCR3 -- output compare register */
|
2013-06-25 19:34:13 +02:00
|
|
|
s->ocr3 = value;
|
|
|
|
|
|
|
|
/* compute the new timeout */
|
2013-06-25 19:34:13 +02:00
|
|
|
imx_gpt_compute_next_timeout(s, false);
|
2013-06-25 19:34:13 +02:00
|
|
|
|
|
|
|
break;
|
|
|
|
|
2012-07-04 12:43:33 +02:00
|
|
|
default:
|
2013-06-25 19:34:13 +02:00
|
|
|
IPRINTF("Bad offset %x\n", reg);
|
|
|
|
break;
|
2012-07-04 12:43:33 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-06-25 19:34:13 +02:00
|
|
|
static void imx_gpt_timeout(void *opaque)
|
2012-07-04 12:43:33 +02:00
|
|
|
{
|
2013-06-25 19:34:13 +02:00
|
|
|
IMXGPTState *s = IMX_GPT(opaque);
|
2012-07-04 12:43:33 +02:00
|
|
|
|
2013-06-25 19:34:13 +02:00
|
|
|
DPRINTF("\n");
|
2012-07-04 12:43:33 +02:00
|
|
|
|
2013-06-25 19:34:13 +02:00
|
|
|
s->sr |= s->next_int;
|
|
|
|
s->next_int = 0;
|
|
|
|
|
2013-06-25 19:34:13 +02:00
|
|
|
imx_gpt_compute_next_timeout(s, true);
|
2012-07-04 12:43:33 +02:00
|
|
|
|
2013-06-25 19:34:13 +02:00
|
|
|
imx_gpt_update_int(s);
|
2013-06-25 19:34:13 +02:00
|
|
|
|
|
|
|
if (s->freq && (s->cr & GPT_CR_EN)) {
|
|
|
|
ptimer_run(s->timer, 1);
|
|
|
|
}
|
2012-07-04 12:43:33 +02:00
|
|
|
}
|
|
|
|
|
2013-06-25 19:34:13 +02:00
|
|
|
static const MemoryRegionOps imx_gpt_ops = {
|
|
|
|
.read = imx_gpt_read,
|
|
|
|
.write = imx_gpt_write,
|
2012-07-04 12:43:33 +02:00
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
};
|
|
|
|
|
|
|
|
|
2013-06-25 19:34:13 +02:00
|
|
|
static void imx_gpt_realize(DeviceState *dev, Error **errp)
|
2012-07-04 12:43:33 +02:00
|
|
|
{
|
2013-06-25 19:34:13 +02:00
|
|
|
IMXGPTState *s = IMX_GPT(dev);
|
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
2012-07-04 12:43:33 +02:00
|
|
|
QEMUBH *bh;
|
|
|
|
|
2013-06-25 19:34:13 +02:00
|
|
|
sysbus_init_irq(sbd, &s->irq);
|
2013-06-07 03:25:08 +02:00
|
|
|
memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpt_ops, s, TYPE_IMX_GPT,
|
2012-07-04 12:43:33 +02:00
|
|
|
0x00001000);
|
2013-06-25 19:34:13 +02:00
|
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
2012-07-04 12:43:33 +02:00
|
|
|
|
2013-06-25 19:34:13 +02:00
|
|
|
bh = qemu_bh_new(imx_gpt_timeout, s);
|
2012-07-04 12:43:33 +02:00
|
|
|
s->timer = ptimer_init(bh);
|
|
|
|
}
|
|
|
|
|
2013-06-25 19:34:13 +02:00
|
|
|
void imx_timerg_create(const hwaddr addr, qemu_irq irq, DeviceState *ccm)
|
2012-07-04 12:43:33 +02:00
|
|
|
{
|
2013-06-25 19:34:13 +02:00
|
|
|
IMXGPTState *pp;
|
2012-07-04 12:43:33 +02:00
|
|
|
DeviceState *dev;
|
|
|
|
|
2013-06-25 19:34:13 +02:00
|
|
|
dev = sysbus_create_simple(TYPE_IMX_GPT, addr, irq);
|
2013-06-25 19:34:13 +02:00
|
|
|
pp = IMX_GPT(dev);
|
2012-07-04 12:43:33 +02:00
|
|
|
pp->ccm = ccm;
|
|
|
|
}
|
|
|
|
|
2013-06-25 19:34:13 +02:00
|
|
|
static void imx_gpt_class_init(ObjectClass *klass, void *data)
|
2012-07-04 12:43:33 +02:00
|
|
|
{
|
2013-06-25 19:34:13 +02:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
|
|
|
|
dc->realize = imx_gpt_realize;
|
|
|
|
dc->reset = imx_gpt_reset;
|
|
|
|
dc->vmsd = &vmstate_imx_timer_gpt;
|
2012-07-04 12:43:33 +02:00
|
|
|
dc->desc = "i.MX general timer";
|
|
|
|
}
|
|
|
|
|
2013-06-25 19:34:13 +02:00
|
|
|
static const TypeInfo imx_gpt_info = {
|
2013-06-25 19:34:13 +02:00
|
|
|
.name = TYPE_IMX_GPT,
|
2012-07-04 12:43:33 +02:00
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
2013-06-25 19:34:13 +02:00
|
|
|
.instance_size = sizeof(IMXGPTState),
|
|
|
|
.class_init = imx_gpt_class_init,
|
2012-07-04 12:43:33 +02:00
|
|
|
};
|
|
|
|
|
2013-06-25 19:34:13 +02:00
|
|
|
static void imx_gpt_register_types(void)
|
2012-07-04 12:43:33 +02:00
|
|
|
{
|
2013-06-25 19:34:13 +02:00
|
|
|
type_register_static(&imx_gpt_info);
|
2012-07-04 12:43:33 +02:00
|
|
|
}
|
|
|
|
|
2013-06-25 19:34:13 +02:00
|
|
|
type_init(imx_gpt_register_types)
|