target/arm: Decode t32 simd 3reg and 2reg_scalar extension
Happily, the bits are in the same places compared to a32. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180228193125.20577-16-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -10774,7 +10774,19 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
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default_exception_el(s));
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default_exception_el(s));
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break;
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break;
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}
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}
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if (((insn >> 24) & 3) == 3) {
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if ((insn & 0xfe000a00) == 0xfc000800
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&& arm_dc_feature(s, ARM_FEATURE_V8)) {
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/* The Thumb2 and ARM encodings are identical. */
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if (disas_neon_insn_3same_ext(s, insn)) {
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goto illegal_op;
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}
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} else if ((insn & 0xff000a00) == 0xfe000800
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&& arm_dc_feature(s, ARM_FEATURE_V8)) {
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/* The Thumb2 and ARM encodings are identical. */
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if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
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goto illegal_op;
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}
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} else if (((insn >> 24) & 3) == 3) {
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/* Translate into the equivalent ARM encoding. */
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/* Translate into the equivalent ARM encoding. */
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insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);
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insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);
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if (disas_neon_data_insn(s, insn)) {
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if (disas_neon_data_insn(s, insn)) {
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