target/i386/hvf: add rdmsr 35H MSR_CORE_THREAD_COUNT
Some guests (ex. Darwin-XNU) can attemp to read this MSR to retrieve and validate CPU topology comparing it to ACPI MADT content MSR description from Intel Manual: 35H: MSR_CORE_THREAD_COUNT: Configured State of Enabled Processor Core Count and Logical Processor Count Bits 15:0 THREAD_COUNT The number of logical processors that are currently enabled in the physical package Bits 31:16 Core_COUNT The number of processor cores that are currently enabled in the physical package Bits 63:32 Reserved Signed-off-by: Vladislav Yaroshchuk <yaroshchuk2000@gmail.com> Message-Id: <20210113205323.33310-1-yaroshchuk2000@gmail.com> [RB: reordered MSR definition and dropped u suffix from shift offset] Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -368,6 +368,7 @@ typedef enum X86Seg {
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#define MSR_IA32_SMBASE 0x9e
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#define MSR_SMI_COUNT 0x34
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#define MSR_CORE_THREAD_COUNT 0x35
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#define MSR_MTRRcap 0xfe
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#define MSR_MTRRcap_VCNT 8
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#define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
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@ -668,6 +668,7 @@ void simulate_rdmsr(struct CPUState *cpu)
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{
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X86CPU *x86_cpu = X86_CPU(cpu);
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CPUX86State *env = &x86_cpu->env;
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CPUState *cs = env_cpu(env);
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uint32_t msr = ECX(env);
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uint64_t val = 0;
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@ -745,6 +746,10 @@ void simulate_rdmsr(struct CPUState *cpu)
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case MSR_MTRRdefType:
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val = env->mtrr_deftype;
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break;
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case MSR_CORE_THREAD_COUNT:
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val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */
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val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */
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break;
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default:
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/* fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr); */
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val = 0;
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