haraldwolff/qemu-patch-raspberry4
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endianness fix

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1588 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard 2005-10-30 20:49:44 +00:00
parent aab3309407
commit 02aab46a36
1 changed files with 54 additions and 26 deletions
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80
target-sparc/op_helper.c
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@ -256,11 +256,18 @@ void helper_ld_asi(int asi, int size, int sign)
} }
break; break;
case 0x20 ... 0x2f: /* MMU passthrough */ case 0x20 ... 0x2f: /* MMU passthrough */
cpu_physical_memory_read(T0, (void *) &ret, size); switch(size) {
if (size == 4) case 1:
tswap32s(&ret); ret = ldub_phys(T0);
else if (size == 2) break;
tswap16s((uint16_t *)&ret); case 2:
ret = lduw_phys(T0 & ~1);
break;
default:
case 4:
ret = ldl_phys(T0 & ~3);
break;
}
break; break;
default: default:
ret = 0; ret = 0;
@ -369,12 +376,18 @@ void helper_st_asi(int asi, int size, int sign)
return; return;
case 0x20 ... 0x2f: /* MMU passthrough */ case 0x20 ... 0x2f: /* MMU passthrough */
{ {
uint32_t temp = T1; switch(size) {
if (size == 4) case 1:
tswap32s(&temp); stb_phys(T0, T1);
else if (size == 2) break;
tswap16s((uint16_t *)&temp); case 2:
cpu_physical_memory_write(T0, (void *) &temp, size); stw_phys(T0 & ~1, T1);
break;
case 4:
default:
stl_phys(T0 & ~3, T1);
break;
}
} }
return; return;
default: default:
@ -395,13 +408,21 @@ void helper_ld_asi(int asi, int size, int sign)
case 0x14: // Bypass case 0x14: // Bypass
case 0x15: // Bypass, non-cacheable case 0x15: // Bypass, non-cacheable
{ {
cpu_physical_memory_read(T0, (void *) &ret, size); switch(size) {
if (size == 8) case 1:
tswap64s(&ret); ret = ldub_phys(T0);
if (size == 4) break;
tswap32s((uint32_t *)&ret); case 2:
else if (size == 2) ret = lduw_phys(T0 & ~1);
tswap16s((uint16_t *)&ret); break;
case 4:
ret = ldl_phys(T0 & ~3);
break;
default:
case 8:
ret = ldq_phys(T0 & ~7);
break;
}
break; break;
} }
case 0x04: // Nucleus case 0x04: // Nucleus
@ -503,14 +524,21 @@ void helper_st_asi(int asi, int size, int sign)
case 0x14: // Bypass case 0x14: // Bypass
case 0x15: // Bypass, non-cacheable case 0x15: // Bypass, non-cacheable
{ {
target_ulong temp = T1; switch(size) {
if (size == 8) case 1:
tswap64s(&temp); stb_phys(T0, T1);
else if (size == 4) break;
tswap32s((uint32_t *)&temp); case 2:
else if (size == 2) stw_phys(T0 & ~1, T1);
tswap16s((uint16_t *)&temp); break;
cpu_physical_memory_write(T0, (void *) &temp, size); case 4:
stl_phys(T0 & ~3, T1);
break;
case 8:
default:
stq_phys(T0 & ~7, T1);
break;
}
} }
return; return;
case 0x04: // Nucleus case 0x04: // Nucleus