hw/char/pl011: Add trace events
Add some trace events for the pl011 UART model. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1476294876-12340-5-git-send-email-peter.maydell@linaro.org
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081b1b98b7
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041ac05672
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@ -11,6 +11,7 @@
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#include "hw/sysbus.h"
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#include "hw/sysbus.h"
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#include "sysemu/char.h"
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#include "sysemu/char.h"
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#include "qemu/log.h"
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#include "qemu/log.h"
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#include "trace.h"
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#define TYPE_PL011 "pl011"
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#define TYPE_PL011 "pl011"
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#define PL011(obj) OBJECT_CHECK(PL011State, (obj), TYPE_PL011)
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#define PL011(obj) OBJECT_CHECK(PL011State, (obj), TYPE_PL011)
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@ -58,6 +59,7 @@ static void pl011_update(PL011State *s)
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uint32_t flags;
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uint32_t flags;
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flags = s->int_level & s->int_enabled;
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flags = s->int_level & s->int_enabled;
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trace_pl011_irq_state(flags != 0);
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qemu_set_irq(s->irq, flags != 0);
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qemu_set_irq(s->irq, flags != 0);
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}
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}
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@ -66,10 +68,8 @@ static uint64_t pl011_read(void *opaque, hwaddr offset,
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{
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{
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PL011State *s = (PL011State *)opaque;
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PL011State *s = (PL011State *)opaque;
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uint32_t c;
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uint32_t c;
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uint64_t r;
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if (offset >= 0xfe0 && offset < 0x1000) {
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return s->id[(offset - 0xfe0) >> 2];
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}
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switch (offset >> 2) {
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switch (offset >> 2) {
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case 0: /* UARTDR */
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case 0: /* UARTDR */
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s->flags &= ~PL011_FLAG_RXFF;
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s->flags &= ~PL011_FLAG_RXFF;
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@ -84,41 +84,62 @@ static uint64_t pl011_read(void *opaque, hwaddr offset,
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}
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}
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if (s->read_count == s->read_trigger - 1)
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if (s->read_count == s->read_trigger - 1)
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s->int_level &= ~ PL011_INT_RX;
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s->int_level &= ~ PL011_INT_RX;
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trace_pl011_read_fifo(s->read_count);
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s->rsr = c >> 8;
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s->rsr = c >> 8;
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pl011_update(s);
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pl011_update(s);
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if (s->chr) {
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if (s->chr) {
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qemu_chr_accept_input(s->chr);
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qemu_chr_accept_input(s->chr);
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}
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}
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return c;
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r = c;
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break;
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case 1: /* UARTRSR */
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case 1: /* UARTRSR */
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return s->rsr;
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r = s->rsr;
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break;
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case 6: /* UARTFR */
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case 6: /* UARTFR */
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return s->flags;
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r = s->flags;
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break;
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case 8: /* UARTILPR */
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case 8: /* UARTILPR */
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return s->ilpr;
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r = s->ilpr;
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break;
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case 9: /* UARTIBRD */
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case 9: /* UARTIBRD */
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return s->ibrd;
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r = s->ibrd;
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break;
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case 10: /* UARTFBRD */
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case 10: /* UARTFBRD */
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return s->fbrd;
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r = s->fbrd;
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break;
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case 11: /* UARTLCR_H */
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case 11: /* UARTLCR_H */
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return s->lcr;
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r = s->lcr;
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break;
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case 12: /* UARTCR */
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case 12: /* UARTCR */
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return s->cr;
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r = s->cr;
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break;
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case 13: /* UARTIFLS */
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case 13: /* UARTIFLS */
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return s->ifl;
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r = s->ifl;
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break;
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case 14: /* UARTIMSC */
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case 14: /* UARTIMSC */
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return s->int_enabled;
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r = s->int_enabled;
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break;
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case 15: /* UARTRIS */
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case 15: /* UARTRIS */
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return s->int_level;
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r = s->int_level;
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break;
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case 16: /* UARTMIS */
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case 16: /* UARTMIS */
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return s->int_level & s->int_enabled;
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r = s->int_level & s->int_enabled;
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break;
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case 18: /* UARTDMACR */
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case 18: /* UARTDMACR */
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return s->dmacr;
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r = s->dmacr;
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break;
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case 0x3f8 ... 0x400:
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r = s->id[(offset - 0xfe0) >> 2];
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break;
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default:
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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qemu_log_mask(LOG_GUEST_ERROR,
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"pl011_read: Bad offset %x\n", (int)offset);
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"pl011_read: Bad offset %x\n", (int)offset);
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return 0;
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r = 0;
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break;
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}
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}
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trace_pl011_read(offset, r);
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return r;
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}
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}
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static void pl011_set_read_trigger(PL011State *s)
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static void pl011_set_read_trigger(PL011State *s)
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@ -141,6 +162,8 @@ static void pl011_write(void *opaque, hwaddr offset,
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PL011State *s = (PL011State *)opaque;
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PL011State *s = (PL011State *)opaque;
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unsigned char ch;
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unsigned char ch;
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trace_pl011_write(offset, value);
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switch (offset >> 2) {
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switch (offset >> 2) {
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case 0: /* UARTDR */
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case 0: /* UARTDR */
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/* ??? Check if transmitter is enabled. */
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/* ??? Check if transmitter is enabled. */
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@ -207,11 +230,15 @@ static void pl011_write(void *opaque, hwaddr offset,
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static int pl011_can_receive(void *opaque)
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static int pl011_can_receive(void *opaque)
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{
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{
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PL011State *s = (PL011State *)opaque;
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PL011State *s = (PL011State *)opaque;
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int r;
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if (s->lcr & 0x10)
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if (s->lcr & 0x10) {
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return s->read_count < 16;
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r = s->read_count < 16;
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else
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} else {
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return s->read_count < 1;
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r = s->read_count < 1;
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}
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trace_pl011_can_receive(s->lcr, s->read_count, r);
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return r;
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}
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}
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static void pl011_put_fifo(void *opaque, uint32_t value)
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static void pl011_put_fifo(void *opaque, uint32_t value)
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@ -225,7 +252,9 @@ static void pl011_put_fifo(void *opaque, uint32_t value)
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s->read_fifo[slot] = value;
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s->read_fifo[slot] = value;
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s->read_count++;
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s->read_count++;
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s->flags &= ~PL011_FLAG_RXFE;
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s->flags &= ~PL011_FLAG_RXFE;
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trace_pl011_put_fifo(value, s->read_count);
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if (!(s->lcr & 0x10) || s->read_count == 16) {
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if (!(s->lcr & 0x10) || s->read_count == 16) {
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trace_pl011_put_fifo_full();
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s->flags |= PL011_FLAG_RXFF;
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s->flags |= PL011_FLAG_RXFF;
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}
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}
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if (s->read_count == s->read_trigger) {
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if (s->read_count == s->read_trigger) {
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@ -47,3 +47,12 @@ escc_sunkbd_event_in(int ch, const char *name, int down) "QKeyCode 0x%2.2x [%s],
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escc_sunkbd_event_out(int ch) "Translated keycode 0x%2.2x"
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escc_sunkbd_event_out(int ch) "Translated keycode 0x%2.2x"
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escc_kbd_command(int val) "Command %d"
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escc_kbd_command(int val) "Command %d"
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escc_sunmouse_event(int dx, int dy, int buttons_state) "dx=%d dy=%d buttons=%01x"
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escc_sunmouse_event(int dx, int dy, int buttons_state) "dx=%d dy=%d buttons=%01x"
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# hw/char/pl011.c
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pl011_irq_state(int level) "irq state %d"
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pl011_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
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pl011_read_fifo(int read_count) "FIFO read, read_count now %d"
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pl011_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
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pl011_can_receive(uint32_t lcr, int read_count, int r) "LCR %08x read_count %d returning %d"
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pl011_put_fifo(uint32_t c, int read_count) "new char 0x%x read_count now %d"
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pl011_put_fifo_full(void) "FIFO now full, RXFF set"
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