target-tilegx: Handle basic load and store instructions
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
7f41a8d672
commit
0426335d4f
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@ -213,12 +213,27 @@ static void gen_dblaligni(TCGv tdest, TCGv tsrca, TCGv tsrcb, int shr)
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tcg_temp_free(t0);
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}
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static TileExcp gen_st_opcode(DisasContext *dc, unsigned dest, unsigned srca,
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unsigned srcb, TCGMemOp memop, const char *name)
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{
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if (dest) {
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return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
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}
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tcg_gen_qemu_st_tl(load_gr(dc, srcb), load_gr(dc, srca),
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dc->mmuidx, memop);
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qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", name,
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reg_names[srca], reg_names[srcb]);
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return TILEGX_EXCP_NONE;
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}
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static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
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unsigned dest, unsigned srca)
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{
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TCGv tdest, tsrca;
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const char *mnemonic;
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TCGMemOp memop;
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/* Eliminate nops before doing anything else. */
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switch (opext) {
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@ -275,21 +290,70 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
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case OE_RR_Y1(JRP):
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case OE_RR_X1(JR):
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case OE_RR_Y1(JR):
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return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
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case OE_RR_X1(LD1S):
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memop = MO_SB;
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mnemonic = "ld1s";
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goto do_load;
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case OE_RR_X1(LD1U):
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memop = MO_UB;
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mnemonic = "ld1u";
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goto do_load;
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case OE_RR_X1(LD2S):
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memop = MO_TESW;
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mnemonic = "ld2s";
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goto do_load;
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case OE_RR_X1(LD2U):
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memop = MO_TEUW;
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mnemonic = "ld2u";
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goto do_load;
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case OE_RR_X1(LD4S):
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memop = MO_TESL;
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mnemonic = "ld4s";
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goto do_load;
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case OE_RR_X1(LD4U):
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case OE_RR_X1(LDNA):
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memop = MO_TEUL;
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mnemonic = "ld4u";
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goto do_load;
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case OE_RR_X1(LDNT1S):
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memop = MO_SB;
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mnemonic = "ldnt1s";
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goto do_load;
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case OE_RR_X1(LDNT1U):
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memop = MO_UB;
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mnemonic = "ldnt1u";
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goto do_load;
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case OE_RR_X1(LDNT2S):
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memop = MO_TESW;
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mnemonic = "ldnt2s";
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goto do_load;
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case OE_RR_X1(LDNT2U):
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memop = MO_TEUW;
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mnemonic = "ldnt2u";
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goto do_load;
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case OE_RR_X1(LDNT4S):
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memop = MO_TESL;
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mnemonic = "ldnt4s";
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goto do_load;
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case OE_RR_X1(LDNT4U):
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memop = MO_TEUL;
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mnemonic = "ldnt4u";
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goto do_load;
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case OE_RR_X1(LDNT):
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memop = MO_TEQ;
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mnemonic = "ldnt";
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goto do_load;
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case OE_RR_X1(LD):
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memop = MO_TEQ;
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mnemonic = "ld";
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do_load:
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tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
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break;
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case OE_RR_X1(LDNA):
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tcg_gen_andi_tl(tdest, tsrca, ~7);
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tcg_gen_qemu_ld_tl(tdest, tdest, dc->mmuidx, MO_TEQ);
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mnemonic = "ldna";
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break;
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case OE_RR_X1(LNK):
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case OE_RR_Y1(LNK):
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case OE_RR_X1(MF):
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@ -583,15 +647,6 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
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gen_helper_shufflebytes(tdest, load_gr(dc, dest), tsrca, tsrca);
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mnemonic = "shufflebytes";
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break;
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case OE_RRR(ST1, 0, X1):
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case OE_RRR(ST2, 0, X1):
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case OE_RRR(ST4, 0, X1):
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case OE_RRR(STNT1, 0, X1):
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case OE_RRR(STNT2, 0, X1):
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case OE_RRR(STNT4, 0, X1):
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case OE_RRR(STNT, 0, X1):
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case OE_RRR(ST, 0, X1):
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return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
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case OE_RRR(SUBXSC, 0, X0):
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case OE_RRR(SUBXSC, 0, X1):
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gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_sub_tl);
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@ -1098,27 +1153,55 @@ static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle)
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unsigned srca = get_SrcA_Y2(bundle);
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unsigned srcbdest = get_SrcBDest_Y2(bundle);
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const char *mnemonic;
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TCGMemOp memop;
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switch (OEY2(opc, mode)) {
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case OEY2(LD1S_OPCODE_Y2, MODE_OPCODE_YA2):
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memop = MO_SB;
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mnemonic = "ld1s";
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goto do_load;
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case OEY2(LD1U_OPCODE_Y2, MODE_OPCODE_YA2):
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memop = MO_UB;
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mnemonic = "ld1u";
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goto do_load;
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case OEY2(LD2S_OPCODE_Y2, MODE_OPCODE_YA2):
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memop = MO_TESW;
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mnemonic = "ld2s";
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goto do_load;
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case OEY2(LD2U_OPCODE_Y2, MODE_OPCODE_YA2):
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memop = MO_TEUW;
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mnemonic = "ld2u";
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goto do_load;
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case OEY2(LD4S_OPCODE_Y2, MODE_OPCODE_YB2):
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memop = MO_TESL;
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mnemonic = "ld4s";
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goto do_load;
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case OEY2(LD4U_OPCODE_Y2, MODE_OPCODE_YB2):
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memop = MO_TEUL;
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mnemonic = "ld4u";
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goto do_load;
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case OEY2(LD_OPCODE_Y2, MODE_OPCODE_YB2):
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memop = MO_TEQ;
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mnemonic = "ld";
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do_load:
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tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca),
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dc->mmuidx, memop);
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qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
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reg_names[srcbdest], reg_names[srca]);
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return TILEGX_EXCP_NONE;
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case OEY2(ST1_OPCODE_Y2, MODE_OPCODE_YC2):
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return gen_st_opcode(dc, 0, srca, srcbdest, MO_UB, "st1");
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case OEY2(ST2_OPCODE_Y2, MODE_OPCODE_YC2):
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return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEUW, "st2");
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case OEY2(ST4_OPCODE_Y2, MODE_OPCODE_YC2):
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return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEUL, "st4");
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case OEY2(ST_OPCODE_Y2, MODE_OPCODE_YC2):
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return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEQ, "st");
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default:
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return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
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}
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qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
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reg_names[srca], reg_names[srcbdest]);
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return TILEGX_EXCP_NONE;
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}
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static TileExcp decode_x0(DisasContext *dc, tilegx_bundle_bits bundle)
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@ -1177,11 +1260,28 @@ static TileExcp decode_x1(DisasContext *dc, tilegx_bundle_bits bundle)
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switch (opc) {
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case RRR_0_OPCODE_X1:
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ext = get_RRROpcodeExtension_X1(bundle);
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if (ext == UNARY_RRR_0_OPCODE_X1) {
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srcb = get_SrcB_X1(bundle);
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switch (ext) {
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case UNARY_RRR_0_OPCODE_X1:
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ext = get_UnaryOpcodeExtension_X1(bundle);
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return gen_rr_opcode(dc, OE(opc, ext, X1), dest, srca);
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case ST1_RRR_0_OPCODE_X1:
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return gen_st_opcode(dc, dest, srca, srcb, MO_UB, "st1");
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case ST2_RRR_0_OPCODE_X1:
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return gen_st_opcode(dc, dest, srca, srcb, MO_TEUW, "st2");
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case ST4_RRR_0_OPCODE_X1:
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return gen_st_opcode(dc, dest, srca, srcb, MO_TEUL, "st4");
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case STNT1_RRR_0_OPCODE_X1:
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return gen_st_opcode(dc, dest, srca, srcb, MO_UB, "stnt1");
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case STNT2_RRR_0_OPCODE_X1:
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return gen_st_opcode(dc, dest, srca, srcb, MO_TEUW, "stnt2");
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case STNT4_RRR_0_OPCODE_X1:
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return gen_st_opcode(dc, dest, srca, srcb, MO_TEUL, "stnt4");
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case STNT_RRR_0_OPCODE_X1:
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return gen_st_opcode(dc, dest, srca, srcb, MO_TEQ, "stnt");
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case ST_RRR_0_OPCODE_X1:
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return gen_st_opcode(dc, dest, srca, srcb, MO_TEQ, "st");
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}
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srcb = get_SrcB_X1(bundle);
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return gen_rrr_opcode(dc, OE(opc, ext, X1), dest, srca, srcb);
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case SHIFT_OPCODE_X1:
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