nvic: Add missing code for writing SHCSR.HARDFAULTPENDED bit
When we added support for the new SHCSR bits in v8M in commit
437d59c17e
the code to support writing to the new HARDFAULTPENDED
bit was accidentally only added for non-secure writes; the
secure banked version of the bit should also be writable.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1506092407-26985-21-git-send-email-peter.maydell@linaro.org
This commit is contained in:
parent
b81ac0eb63
commit
04829ce334
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@ -1230,6 +1230,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
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s->sec_vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
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s->sec_vectors[ARMV7M_EXCP_USAGE].enabled =
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(value & (1 << 18)) != 0;
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s->sec_vectors[ARMV7M_EXCP_HARD].pending = (value & (1 << 21)) != 0;
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/* SecureFault not banked, but RAZ/WI to NS */
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s->vectors[ARMV7M_EXCP_SECURE].active = (value & (1 << 4)) != 0;
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s->vectors[ARMV7M_EXCP_SECURE].enabled = (value & (1 << 19)) != 0;
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