target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions
Implement the floating-point-to-integer conversion instructions FCVT[NMAPZ][SU] in the 2-reg-misc and scalar-2-reg-misc categories. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-10-git-send-email-peter.maydell@linaro.org
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@ -6683,11 +6683,14 @@ static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn)
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}
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static void handle_2misc_64(DisasContext *s, int opcode, bool u,
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TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
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TCGv_i64 tcg_rd, TCGv_i64 tcg_rn,
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TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus)
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{
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/* Handle 64->64 opcodes which are shared between the scalar and
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* vector 2-reg-misc groups. We cover every integer opcode where size == 3
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* is valid in either group and also the double-precision fp ops.
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* The caller only need provide tcg_rmode and tcg_fpstatus if the op
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* requires them.
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*/
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TCGCond cond;
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@ -6741,6 +6744,28 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
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case 0x7f: /* FSQRT */
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gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, cpu_env);
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break;
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case 0x1a: /* FCVTNS */
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case 0x1b: /* FCVTMS */
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case 0x1c: /* FCVTAS */
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case 0x3a: /* FCVTPS */
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case 0x3b: /* FCVTZS */
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{
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TCGv_i32 tcg_shift = tcg_const_i32(0);
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gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
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tcg_temp_free_i32(tcg_shift);
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break;
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}
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case 0x5a: /* FCVTNU */
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case 0x5b: /* FCVTMU */
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case 0x5c: /* FCVTAU */
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case 0x7a: /* FCVTPU */
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case 0x7b: /* FCVTZU */
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{
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TCGv_i32 tcg_shift = tcg_const_i32(0);
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gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
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tcg_temp_free_i32(tcg_shift);
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break;
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}
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default:
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g_assert_not_reached();
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}
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@ -6868,6 +6893,10 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
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int opcode = extract32(insn, 12, 5);
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int size = extract32(insn, 22, 2);
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bool u = extract32(insn, 29, 1);
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bool is_fcvt = false;
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int rmode;
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TCGv_i32 tcg_rmode;
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TCGv_ptr tcg_fpstatus;
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switch (opcode) {
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case 0xa: /* CMLT */
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@ -6909,17 +6938,24 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
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}
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case 0x1a: /* FCVTNS */
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case 0x1b: /* FCVTMS */
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case 0x1c: /* FCVTAS */
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case 0x3a: /* FCVTPS */
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case 0x3b: /* FCVTZS */
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case 0x5a: /* FCVTNU */
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case 0x5b: /* FCVTMU */
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case 0x7a: /* FCVTPU */
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case 0x7b: /* FCVTZU */
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is_fcvt = true;
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rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
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break;
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case 0x1c: /* FCVTAS */
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case 0x5c: /* FCVTAU */
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/* TIEAWAY doesn't fit in the usual rounding mode encoding */
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is_fcvt = true;
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rmode = FPROUNDING_TIEAWAY;
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break;
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case 0x3d: /* FRECPE */
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case 0x3f: /* FRECPX */
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case 0x56: /* FCVTXN, FCVTXN2 */
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case 0x5a: /* FCVTNU */
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case 0x5b: /* FCVTMU */
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case 0x5c: /* FCVTAU */
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case 0x7a: /* FCVTPU */
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case 0x7b: /* FCVTZU */
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case 0x7d: /* FRSQRTE */
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unsupported_encoding(s, insn);
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return;
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@ -6938,18 +6974,66 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
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return;
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}
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if (is_fcvt) {
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tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
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gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
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tcg_fpstatus = get_fpstatus_ptr();
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} else {
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TCGV_UNUSED_I32(tcg_rmode);
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TCGV_UNUSED_PTR(tcg_fpstatus);
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}
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if (size == 3) {
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TCGv_i64 tcg_rn = read_fp_dreg(s, rn);
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TCGv_i64 tcg_rd = tcg_temp_new_i64();
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handle_2misc_64(s, opcode, u, tcg_rd, tcg_rn);
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handle_2misc_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rmode, tcg_fpstatus);
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write_fp_dreg(s, rd, tcg_rd);
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tcg_temp_free_i64(tcg_rd);
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tcg_temp_free_i64(tcg_rn);
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} else {
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/* the 'size might not be 64' ops aren't implemented yet */
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} else if (size == 2) {
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TCGv_i32 tcg_rn = read_fp_sreg(s, rn);
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TCGv_i32 tcg_rd = tcg_temp_new_i32();
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switch (opcode) {
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case 0x1a: /* FCVTNS */
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case 0x1b: /* FCVTMS */
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case 0x1c: /* FCVTAS */
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case 0x3a: /* FCVTPS */
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case 0x3b: /* FCVTZS */
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{
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TCGv_i32 tcg_shift = tcg_const_i32(0);
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gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
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tcg_temp_free_i32(tcg_shift);
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break;
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}
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case 0x5a: /* FCVTNU */
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case 0x5b: /* FCVTMU */
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case 0x5c: /* FCVTAU */
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case 0x7a: /* FCVTPU */
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case 0x7b: /* FCVTZU */
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{
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TCGv_i32 tcg_shift = tcg_const_i32(0);
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gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
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tcg_temp_free_i32(tcg_shift);
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break;
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}
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default:
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g_assert_not_reached();
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}
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write_fp_sreg(s, rd, tcg_rd);
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tcg_temp_free_i32(tcg_rd);
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tcg_temp_free_i32(tcg_rn);
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} else {
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g_assert_not_reached();
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}
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if (is_fcvt) {
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gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
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tcg_temp_free_i32(tcg_rmode);
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tcg_temp_free_ptr(tcg_fpstatus);
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}
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}
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/* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
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@ -8573,6 +8657,11 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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bool is_q = extract32(insn, 30, 1);
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int rn = extract32(insn, 5, 5);
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int rd = extract32(insn, 0, 5);
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bool need_fpstatus = false;
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bool need_rmode = false;
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int rmode = -1;
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TCGv_i32 tcg_rmode;
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TCGv_ptr tcg_fpstatus;
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switch (opcode) {
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case 0x0: /* REV64, REV32 */
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@ -8691,28 +8780,44 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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return;
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}
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break;
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case 0x1a: /* FCVTNS */
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case 0x1b: /* FCVTMS */
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case 0x3a: /* FCVTPS */
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case 0x3b: /* FCVTZS */
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case 0x5a: /* FCVTNU */
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case 0x5b: /* FCVTMU */
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case 0x7a: /* FCVTPU */
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case 0x7b: /* FCVTZU */
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need_fpstatus = true;
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need_rmode = true;
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rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
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if (size == 3 && !is_q) {
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unallocated_encoding(s);
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return;
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}
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break;
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case 0x5c: /* FCVTAU */
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case 0x1c: /* FCVTAS */
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need_fpstatus = true;
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need_rmode = true;
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rmode = FPROUNDING_TIEAWAY;
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if (size == 3 && !is_q) {
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unallocated_encoding(s);
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return;
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}
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break;
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case 0x16: /* FCVTN, FCVTN2 */
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case 0x17: /* FCVTL, FCVTL2 */
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case 0x18: /* FRINTN */
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case 0x19: /* FRINTM */
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case 0x1a: /* FCVTNS */
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case 0x1b: /* FCVTMS */
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case 0x1c: /* FCVTAS */
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case 0x38: /* FRINTP */
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case 0x39: /* FRINTZ */
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case 0x3a: /* FCVTPS */
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case 0x3b: /* FCVTZS */
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case 0x3c: /* URECPE */
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case 0x3d: /* FRECPE */
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case 0x56: /* FCVTXN, FCVTXN2 */
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case 0x58: /* FRINTA */
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case 0x59: /* FRINTX */
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case 0x5a: /* FCVTNU */
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case 0x5b: /* FCVTMU */
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case 0x5c: /* FCVTAU */
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case 0x79: /* FRINTI */
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case 0x7a: /* FCVTPU */
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case 0x7b: /* FCVTZU */
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case 0x7c: /* URSQRTE */
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case 0x7d: /* FRSQRTE */
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unsupported_encoding(s, insn);
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@ -8728,6 +8833,18 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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return;
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}
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if (need_fpstatus) {
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tcg_fpstatus = get_fpstatus_ptr();
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} else {
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TCGV_UNUSED_PTR(tcg_fpstatus);
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}
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if (need_rmode) {
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tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
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gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
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} else {
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TCGV_UNUSED_I32(tcg_rmode);
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}
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if (size == 3) {
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/* All 64-bit element operations can be shared with scalar 2misc */
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int pass;
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read_vec_element(s, tcg_op, rn, pass, MO_64);
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handle_2misc_64(s, opcode, u, tcg_res, tcg_op);
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handle_2misc_64(s, opcode, u, tcg_res, tcg_op,
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tcg_rmode, tcg_fpstatus);
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write_vec_element(s, tcg_res, rd, pass, MO_64);
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@ -8801,6 +8919,30 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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case 0x7f: /* FSQRT */
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gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env);
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break;
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case 0x1a: /* FCVTNS */
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case 0x1b: /* FCVTMS */
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case 0x1c: /* FCVTAS */
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case 0x3a: /* FCVTPS */
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case 0x3b: /* FCVTZS */
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{
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TCGv_i32 tcg_shift = tcg_const_i32(0);
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gen_helper_vfp_tosls(tcg_res, tcg_op,
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tcg_shift, tcg_fpstatus);
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tcg_temp_free_i32(tcg_shift);
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break;
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}
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case 0x5a: /* FCVTNU */
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case 0x5b: /* FCVTMU */
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case 0x5c: /* FCVTAU */
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case 0x7a: /* FCVTPU */
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case 0x7b: /* FCVTZU */
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{
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TCGv_i32 tcg_shift = tcg_const_i32(0);
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gen_helper_vfp_touls(tcg_res, tcg_op,
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tcg_shift, tcg_fpstatus);
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tcg_temp_free_i32(tcg_shift);
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break;
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}
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default:
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g_assert_not_reached();
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}
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if (!is_q) {
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clear_vec_high(s, rd);
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}
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if (need_rmode) {
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gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
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tcg_temp_free_i32(tcg_rmode);
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}
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if (need_fpstatus) {
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tcg_temp_free_ptr(tcg_fpstatus);
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}
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}
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/* C3.6.13 AdvSIMD scalar x indexed element
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