m48t59: register a QOM type for each nvram type we support
As m48t59 devices can only be created with m48t59_init() or m48t59_init_isa(), we know exactly which nvram types are required. Register only those three types. Remove .model and .size properties as they can be infered from nvram name. Rename type to 'isa-*' (and 'sysbus-*') to do like other devices ISA devices (isa-ide, isa-parallel, isa-serial...) Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> CC: Andreas Färber <afaerber@suse.de> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
This commit is contained in:
Hervé Poussineau
Mark Cave-Ayland
parent
72cd63f817
commit
051ddccde2
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@ -2,6 +2,7 @@
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* QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
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*
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* Copyright (c) 2003-2005, 2007 Jocelyn Mayer
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* Copyright (c) 2013 Hervé Poussineau
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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@ -37,12 +38,35 @@
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#define NVRAM_PRINTF(fmt, ...) do { } while (0)
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#endif
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#define TYPE_M48TXX_SYS_BUS "sysbus-m48txx"
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#define M48TXX_SYS_BUS_GET_CLASS(obj) \
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OBJECT_GET_CLASS(M48txxSysBusDeviceClass, (obj), TYPE_M48TXX_SYS_BUS)
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#define M48TXX_SYS_BUS_CLASS(klass) \
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OBJECT_CLASS_CHECK(M48txxSysBusDeviceClass, (klass), TYPE_M48TXX_SYS_BUS)
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#define M48TXX_SYS_BUS(obj) \
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OBJECT_CHECK(M48txxSysBusState, (obj), TYPE_M48TXX_SYS_BUS)
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#define TYPE_M48TXX_ISA "isa-m48txx"
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#define M48TXX_ISA_GET_CLASS(obj) \
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OBJECT_GET_CLASS(M48txxISADeviceClass, (obj), TYPE_M48TXX_ISA)
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#define M48TXX_ISA_CLASS(klass) \
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OBJECT_CLASS_CHECK(M48txxISADeviceClass, (klass), TYPE_M48TXX_ISA)
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#define M48TXX_ISA(obj) \
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OBJECT_CHECK(M48txxISAState, (obj), TYPE_M48TXX_ISA)
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/*
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* The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
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* alarm and a watchdog timer and related control registers. In the
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* PPC platform there is also a nvram lock function.
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*/
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typedef struct M48txxInfo {
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const char *isa_name;
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const char *sysbus_name;
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uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
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uint32_t size;
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} M48txxInfo;
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/*
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* Chipset docs:
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* http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
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@ -54,7 +78,6 @@ struct M48t59State {
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/* Hardware parameters */
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qemu_irq IRQ;
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MemoryRegion iomem;
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uint32_t io_base;
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uint32_t size;
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/* RTC management */
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time_t time_offset;
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@ -72,26 +95,45 @@ struct M48t59State {
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uint8_t lock;
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};
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#define TYPE_ISA_M48T59 "m48t59_isa"
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#define ISA_M48T59(obj) \
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OBJECT_CHECK(M48t59ISAState, (obj), TYPE_ISA_M48T59)
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typedef struct M48t59ISAState {
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typedef struct M48txxISAState {
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ISADevice parent_obj;
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M48t59State state;
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uint32_t io_base;
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MemoryRegion io;
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} M48t59ISAState;
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} M48txxISAState;
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#define SYSBUS_M48T59(obj) \
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OBJECT_CHECK(M48t59SysBusState, (obj), TYPE_SYSBUS_M48T59)
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typedef struct M48txxISADeviceClass {
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ISADeviceClass parent_class;
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M48txxInfo info;
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} M48txxISADeviceClass;
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typedef struct M48t59SysBusState {
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typedef struct M48txxSysBusState {
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SysBusDevice parent_obj;
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M48t59State state;
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MemoryRegion io;
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} M48t59SysBusState;
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} M48txxSysBusState;
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typedef struct M48txxSysBusDeviceClass {
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SysBusDeviceClass parent_class;
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M48txxInfo info;
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} M48txxSysBusDeviceClass;
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static M48txxInfo m48txx_info[] = {
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{
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.sysbus_name = "sysbus-m48t02",
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.model = 2,
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.size = 0x800,
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},{
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.sysbus_name = "sysbus-m48t08",
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.model = 8,
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.size = 0x2000,
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},{
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.isa_name = "isa-m48t59",
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.model = 59,
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.size = 0x2000,
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}
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};
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/* Fake timer functions */
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@ -616,7 +658,7 @@ static void m48t59_reset_common(M48t59State *NVRAM)
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static void m48t59_reset_isa(DeviceState *d)
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{
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M48t59ISAState *isa = ISA_M48T59(d);
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M48txxISAState *isa = M48TXX_ISA(d);
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M48t59State *NVRAM = &isa->state;
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m48t59_reset_common(NVRAM);
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@ -624,7 +666,7 @@ static void m48t59_reset_isa(DeviceState *d)
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static void m48t59_reset_sysbus(DeviceState *d)
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{
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M48t59SysBusState *sys = SYSBUS_M48T59(d);
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M48txxSysBusState *sys = M48TXX_SYS_BUS(d);
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M48t59State *NVRAM = &sys->state;
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m48t59_reset_common(NVRAM);
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@ -646,47 +688,59 @@ M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
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{
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DeviceState *dev;
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SysBusDevice *s;
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M48t59SysBusState *d;
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M48txxSysBusState *d;
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M48t59State *state;
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int i;
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dev = qdev_create(NULL, TYPE_SYSBUS_M48T59);
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qdev_prop_set_uint32(dev, "model", model);
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qdev_prop_set_uint32(dev, "size", size);
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qdev_prop_set_uint32(dev, "io_base", io_base);
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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d = SYSBUS_M48T59(dev);
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state = &d->state;
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sysbus_connect_irq(s, 0, IRQ);
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if (io_base != 0) {
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memory_region_add_subregion(get_system_io(), io_base,
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sysbus_mmio_get_region(dev, 1));
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}
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if (mem_base != 0) {
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sysbus_mmio_map(s, 0, mem_base);
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for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
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if (!m48txx_info[i].sysbus_name ||
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m48txx_info[i].size != size ||
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m48txx_info[i].model != model) {
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continue;
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}
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dev = qdev_create(NULL, m48txx_info[i].sysbus_name);
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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d = M48TXX_SYS_BUS(s);
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state = &d->state;
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sysbus_connect_irq(s, 0, IRQ);
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if (io_base != 0) {
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memory_region_add_subregion(get_system_io(), io_base,
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sysbus_mmio_get_region(s, 1));
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}
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if (mem_base != 0) {
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sysbus_mmio_map(s, 0, mem_base);
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}
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return state;
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}
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return state;
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assert(false);
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return NULL;
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}
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M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
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int model)
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{
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M48t59ISAState *d;
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ISADevice *isadev;
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DeviceState *dev;
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M48t59State *s;
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int i;
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isadev = isa_create(bus, TYPE_ISA_M48T59);
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dev = DEVICE(isadev);
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qdev_prop_set_uint32(dev, "model", model);
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qdev_prop_set_uint32(dev, "size", size);
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qdev_prop_set_uint32(dev, "io_base", io_base);
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qdev_init_nofail(dev);
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d = ISA_M48T59(isadev);
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s = &d->state;
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for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
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if (!m48txx_info[i].isa_name ||
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m48txx_info[i].size != size ||
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m48txx_info[i].model != model) {
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continue;
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}
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return s;
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dev = DEVICE(isa_create(bus, m48txx_info[i].isa_name));
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qdev_prop_set_uint32(dev, "iobase", io_base);
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qdev_init_nofail(dev);
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return &M48TXX_ISA(dev)->state;
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}
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assert(false);
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return NULL;
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}
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static void m48t59_realize_common(M48t59State *s, Error **errp)
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@ -703,27 +757,31 @@ static void m48t59_realize_common(M48t59State *s, Error **errp)
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static void m48t59_isa_realize(DeviceState *dev, Error **errp)
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{
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M48txxISADeviceClass *u = M48TXX_ISA_GET_CLASS(dev);
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ISADevice *isadev = ISA_DEVICE(dev);
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M48t59ISAState *d = ISA_M48T59(dev);
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M48txxISAState *d = M48TXX_ISA(dev);
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M48t59State *s = &d->state;
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s->model = u->info.model;
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s->size = u->info.size;
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isa_init_irq(isadev, &s->IRQ, 8);
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m48t59_realize_common(s, errp);
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memory_region_init_io(&d->io, OBJECT(dev), &m48t59_io_ops, s, "m48t59", 4);
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if (s->io_base != 0) {
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isa_register_ioport(isadev, &d->io, s->io_base);
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if (d->io_base != 0) {
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isa_register_ioport(isadev, &d->io, d->io_base);
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}
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return 0;
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}
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static int m48t59_init1(SysBusDevice *dev)
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{
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M48t59SysBusState *d = SYSBUS_M48T59(dev);
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M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_GET_CLASS(dev);
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M48txxSysBusState *d = M48TXX_SYS_BUS(dev);
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Object *o = OBJECT(dev);
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M48t59State *s = &d->state;
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Error *err = NULL;
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s->model = u->info.model;
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s->size = u->info.size;
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sysbus_init_irq(dev, &s->IRQ);
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memory_region_init_io(&s->iomem, o, &nvram_ops, s, "m48t59.nvram",
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@ -741,13 +799,11 @@ static int m48t59_init1(SysBusDevice *dev)
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}
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static Property m48t59_isa_properties[] = {
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DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1),
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DEFINE_PROP_UINT32("model", M48t59ISAState, state.model, -1),
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DEFINE_PROP_UINT32("io_base", M48t59ISAState, state.io_base, 0),
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DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void m48t59_isa_class_init(ObjectClass *klass, void *data)
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static void m48txx_isa_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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@ -756,41 +812,77 @@ static void m48t59_isa_class_init(ObjectClass *klass, void *data)
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dc->props = m48t59_isa_properties;
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}
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static const TypeInfo m48t59_isa_info = {
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.name = TYPE_ISA_M48T59,
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.parent = TYPE_ISA_DEVICE,
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.instance_size = sizeof(M48t59ISAState),
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.class_init = m48t59_isa_class_init,
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};
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static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data)
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{
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M48txxISADeviceClass *u = M48TXX_ISA_CLASS(klass);
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M48txxInfo *info = data;
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static Property m48t59_properties[] = {
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DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1),
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DEFINE_PROP_UINT32("model", M48t59SysBusState, state.model, -1),
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DEFINE_PROP_UINT32("io_base", M48t59SysBusState, state.io_base, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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u->info = *info;
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}
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static void m48t59_class_init(ObjectClass *klass, void *data)
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static void m48txx_sysbus_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = m48t59_init1;
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dc->reset = m48t59_reset_sysbus;
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dc->props = m48t59_properties;
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}
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static const TypeInfo m48t59_info = {
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.name = TYPE_SYSBUS_M48T59,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(M48t59SysBusState),
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.class_init = m48t59_class_init,
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static void m48txx_sysbus_concrete_class_init(ObjectClass *klass, void *data)
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{
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M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_CLASS(klass);
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M48txxInfo *info = data;
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u->info = *info;
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}
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static const TypeInfo m48txx_sysbus_type_info = {
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.name = TYPE_M48TXX_SYS_BUS,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(M48txxSysBusState),
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.abstract = true,
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.class_init = m48txx_sysbus_class_init,
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};
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static const TypeInfo m48txx_isa_type_info = {
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.name = TYPE_M48TXX_ISA,
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.parent = TYPE_ISA_DEVICE,
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.instance_size = sizeof(M48txxISAState),
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.abstract = true,
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.class_init = m48txx_isa_class_init,
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};
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static void m48t59_register_types(void)
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{
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type_register_static(&m48t59_info);
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type_register_static(&m48t59_isa_info);
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TypeInfo sysbus_type_info = {
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.parent = TYPE_M48TXX_SYS_BUS,
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.class_size = sizeof(M48txxSysBusDeviceClass),
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.class_init = m48txx_sysbus_concrete_class_init,
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};
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TypeInfo isa_type_info = {
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.parent = TYPE_M48TXX_ISA,
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.class_size = sizeof(M48txxISADeviceClass),
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.class_init = m48txx_isa_concrete_class_init,
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};
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int i;
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type_register_static(&m48txx_sysbus_type_info);
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type_register_static(&m48txx_isa_type_info);
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for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
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if (m48txx_info[i].sysbus_name) {
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sysbus_type_info.name = m48txx_info[i].sysbus_name;
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sysbus_type_info.class_data = &m48txx_info[i];
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type_register(&sysbus_type_info);
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}
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if (m48txx_info[i].isa_name) {
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isa_type_info.name = m48txx_info[i].isa_name;
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isa_type_info.class_data = &m48txx_info[i];
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type_register(&isa_type_info);
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}
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}
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}
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type_init(m48t59_register_types)
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