target-arm: Share all common TCG temporaries
This is a bug fix for aarch64. At present, we have branches using
the 32-bit (translate.c) versions of cpu_[NZCV]F, but we set the flags
using the 64-bit (translate-a64.c) versions of cpu_[NZCV]F. From
the view of the TCG code generator, these are unrelated variables.
The bug is hard to see because we currently only read these variables
from branches, and upon reaching a branch TCG will first spill live
variables and then reload the arguments of the branch. Since the
32-bit versions were never live until reaching the branch, we'd re-read
the data that had just been spilled from the 64-bit versions.
There is currently no such problem with the cpu_exclusive_* variables,
but there's no point in tempting fate.
Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-id: 1441909103-24666-2-git-send-email-rth@twiddle.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
(cherry picked from commit 78bcaa3e37
)
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
stable-2.4
parent
0fdf9f756f
commit
052677b2c8
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@ -39,16 +39,9 @@
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static TCGv_i64 cpu_X[32];
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static TCGv_i64 cpu_pc;
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static TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
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/* Load/store exclusive handling */
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static TCGv_i64 cpu_exclusive_addr;
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static TCGv_i64 cpu_exclusive_val;
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static TCGv_i64 cpu_exclusive_high;
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#ifdef CONFIG_USER_ONLY
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static TCGv_i64 cpu_exclusive_test;
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static TCGv_i32 cpu_exclusive_info;
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#endif
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static const char *regnames[] = {
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"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
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@ -104,23 +97,8 @@ void a64_translate_init(void)
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regnames[i]);
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}
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cpu_NF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, NF), "NF");
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cpu_ZF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, ZF), "ZF");
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cpu_CF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, CF), "CF");
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cpu_VF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, VF), "VF");
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cpu_exclusive_addr = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUARMState, exclusive_addr), "exclusive_addr");
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cpu_exclusive_val = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUARMState, exclusive_val), "exclusive_val");
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cpu_exclusive_high = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUARMState, exclusive_high), "exclusive_high");
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#ifdef CONFIG_USER_ONLY
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cpu_exclusive_test = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUARMState, exclusive_test), "exclusive_test");
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cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUARMState, exclusive_info), "exclusive_info");
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#endif
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}
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static inline ARMMMUIdx get_a64_user_mem_index(DisasContext *s)
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@ -64,12 +64,12 @@ TCGv_ptr cpu_env;
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/* We reuse the same 64-bit temporaries for efficiency. */
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static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
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static TCGv_i32 cpu_R[16];
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static TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF;
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static TCGv_i64 cpu_exclusive_addr;
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static TCGv_i64 cpu_exclusive_val;
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TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF;
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TCGv_i64 cpu_exclusive_addr;
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TCGv_i64 cpu_exclusive_val;
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#ifdef CONFIG_USER_ONLY
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static TCGv_i64 cpu_exclusive_test;
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static TCGv_i32 cpu_exclusive_info;
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TCGv_i64 cpu_exclusive_test;
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TCGv_i32 cpu_exclusive_info;
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#endif
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/* FIXME: These should be removed. */
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@ -62,7 +62,15 @@ typedef struct DisasContext {
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TCGv_i64 tmp_a64[TMP_A64_MAX];
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} DisasContext;
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/* Share the TCG temporaries common between 32 and 64 bit modes. */
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extern TCGv_ptr cpu_env;
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extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
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extern TCGv_i64 cpu_exclusive_addr;
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extern TCGv_i64 cpu_exclusive_val;
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#ifdef CONFIG_USER_ONLY
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extern TCGv_i64 cpu_exclusive_test;
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extern TCGv_i32 cpu_exclusive_info;
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#endif
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static inline int arm_dc_feature(DisasContext *dc, int feature)
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{
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