target-ppc: Add xscvqps[d,w]z instructions
xscvqpsdz: VSX Scalar truncate & Convert Quad-Precision format to Signed Doubleword format xscvqpswz: VSX Scalar truncate & Convert Quad-Precision format to Signed Word format Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -2878,6 +2878,46 @@ VSX_CVT_FP_TO_INT(xvcvspsxws, 4, float32, int32, VsrW(i), VsrW(i), 0x80000000U)
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VSX_CVT_FP_TO_INT(xvcvspuxds, 2, float32, uint64, VsrW(2*i), VsrD(i), 0ULL)
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VSX_CVT_FP_TO_INT(xvcvspuxds, 2, float32, uint64, VsrW(2*i), VsrD(i), 0ULL)
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VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, VsrW(i), VsrW(i), 0U)
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VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, VsrW(i), VsrW(i), 0U)
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/* VSX_CVT_FP_TO_INT_VECTOR - VSX floating point to integer conversion
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* op - instruction mnemonic
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* stp - source type (float32 or float64)
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* ttp - target type (int32, uint32, int64 or uint64)
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* sfld - source vsr_t field
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* tfld - target vsr_t field
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* rnan - resulting NaN
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*/
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#define VSX_CVT_FP_TO_INT_VECTOR(op, stp, ttp, sfld, tfld, rnan) \
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void helper_##op(CPUPPCState *env, uint32_t opcode) \
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{ \
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ppc_vsr_t xt, xb; \
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\
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getVSR(rB(opcode) + 32, &xb, env); \
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memset(&xt, 0, sizeof(xt)); \
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\
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if (unlikely(stp##_is_any_nan(xb.sfld))) { \
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if (stp##_is_signaling_nan(xb.sfld, &env->fp_status)) { \
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float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
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} \
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float_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0); \
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xt.tfld = rnan; \
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} else { \
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xt.tfld = stp##_to_##ttp##_round_to_zero(xb.sfld, \
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&env->fp_status); \
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if (env->fp_status.float_exception_flags & float_flag_invalid) { \
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float_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0); \
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} \
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} \
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\
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putVSR(rD(opcode) + 32, &xt, env); \
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float_check_status(env); \
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}
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VSX_CVT_FP_TO_INT_VECTOR(xscvqpsdz, float128, int64, f128, VsrD(0), \
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0x8000000000000000ULL)
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VSX_CVT_FP_TO_INT_VECTOR(xscvqpswz, float128, int32, f128, VsrD(0), \
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0xffffffff80000000ULL)
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/* VSX_CVT_INT_TO_FP - VSX integer to floating point conversion
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/* VSX_CVT_INT_TO_FP - VSX integer to floating point conversion
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* op - instruction mnemonic
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* op - instruction mnemonic
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* nels - number of elements (1, 2 or 4)
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* nels - number of elements (1, 2 or 4)
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@ -432,6 +432,8 @@ DEF_HELPER_2(xscvdpqp, void, env, i32)
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DEF_HELPER_2(xscvdpsp, void, env, i32)
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DEF_HELPER_2(xscvdpsp, void, env, i32)
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DEF_HELPER_2(xscvdpspn, i64, env, i64)
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DEF_HELPER_2(xscvdpspn, i64, env, i64)
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DEF_HELPER_2(xscvqpdp, void, env, i32)
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DEF_HELPER_2(xscvqpdp, void, env, i32)
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DEF_HELPER_2(xscvqpsdz, void, env, i32)
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DEF_HELPER_2(xscvqpswz, void, env, i32)
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DEF_HELPER_2(xscvhpdp, void, env, i32)
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DEF_HELPER_2(xscvhpdp, void, env, i32)
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DEF_HELPER_2(xscvspdp, void, env, i32)
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DEF_HELPER_2(xscvspdp, void, env, i32)
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DEF_HELPER_2(xscvspdpn, i64, env, i64)
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DEF_HELPER_2(xscvspdpn, i64, env, i64)
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@ -811,6 +811,8 @@ GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300)
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GEN_VSX_HELPER_2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300)
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GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
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GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
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GEN_VSX_HELPER_2(xscvqpdp, 0x04, 0x1A, 0x14, PPC2_ISA300)
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GEN_VSX_HELPER_2(xscvqpdp, 0x04, 0x1A, 0x14, PPC2_ISA300)
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GEN_VSX_HELPER_2(xscvqpsdz, 0x04, 0x1A, 0x19, PPC2_ISA300)
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GEN_VSX_HELPER_2(xscvqpswz, 0x04, 0x1A, 0x09, PPC2_ISA300)
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GEN_VSX_HELPER_2(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300)
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GEN_VSX_HELPER_2(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300)
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GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
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GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
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GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
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@ -114,6 +114,8 @@ GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001),
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GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
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GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
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GEN_VSX_XFORM_300_EO(xscvdpqp, 0x04, 0x1A, 0x16, 0x00000001),
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GEN_VSX_XFORM_300_EO(xscvdpqp, 0x04, 0x1A, 0x16, 0x00000001),
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GEN_VSX_XFORM_300_EO(xscvqpdp, 0x04, 0x1A, 0x14, 0x0),
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GEN_VSX_XFORM_300_EO(xscvqpdp, 0x04, 0x1A, 0x14, 0x0),
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GEN_VSX_XFORM_300_EO(xscvqpsdz, 0x04, 0x1A, 0x19, 0x00000001),
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GEN_VSX_XFORM_300_EO(xscvqpswz, 0x04, 0x1A, 0x09, 0x00000001),
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#ifdef TARGET_PPC64
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#ifdef TARGET_PPC64
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GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300),
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GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300),
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