Gumstix 'connex' board support by Thorsten Zitterell.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3667 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
parent
7f1559c644
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@ -499,6 +499,7 @@ VL_OBJS+= ssd0323.o pl061.o
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VL_OBJS+= arm-semi.o
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VL_OBJS+= pxa2xx.o pxa2xx_pic.o pxa2xx_gpio.o pxa2xx_timer.o pxa2xx_dma.o
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VL_OBJS+= pxa2xx_lcd.o pxa2xx_mmci.o pxa2xx_pcmcia.o max111x.o max7310.o
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VL_OBJS+= pflash_cfi01.o gumstix.o
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VL_OBJS+= spitz.o ads7846.o ide.o serial.o nand.o ecc.o wm8750.o
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VL_OBJS+= omap.o omap_lcdc.o omap1_clk.o omap_mmc.o omap_i2c.o
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VL_OBJS+= palm.o tsc210x.o
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73
hw/gumstix.c
Normal file
73
hw/gumstix.c
Normal file
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@ -0,0 +1,73 @@
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/*
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* Gumstix Platforms
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*
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* Copyright (c) 2007 by Thorsten Zitterell <info@bitmux.org>
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*
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* Code based on spitz platform by Andrzej Zaborowski <balrog@zabor.org>
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*
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* This code is licensed under the GNU GPL v2.
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*/
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#include "vl.h"
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static void connex_smc_irq(void *opaque, int line, int level)
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{
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/* Interrupt line of NIC is connected to GPIO line 36 */
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struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque;
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pxa2xx_gpio_set(cpu->gpio, 36, level);
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}
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/* Board init. */
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enum gumstix_model_e { connex };
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static void gumstix_common_init(int ram_size, int vga_ram_size,
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DisplayState *ds, const char *kernel_filename,
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const char *kernel_cmdline, const char *initrd_filename,
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const char *cpu_model, enum gumstix_model_e model)
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{
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struct pxa2xx_state_s *cpu;
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uint32_t gumstix_rom = 0x02000000;
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uint32_t gumstix_ram = 0x08000000;
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if (ram_size < (gumstix_ram + gumstix_rom + PXA2XX_INTERNAL_SIZE)) {
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fprintf(stderr, "This platform requires %i bytes of memory\n",
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gumstix_ram + gumstix_rom + PXA2XX_INTERNAL_SIZE);
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exit(1);
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}
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cpu = pxa255_init(gumstix_ram, ds);
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if (pflash_table[0] == NULL) {
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fprintf(stderr, "A flash image must be given with the "
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"'pflash' parameter\n");
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exit(1);
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}
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if (!pflash_register(0x00000000, gumstix_ram + PXA2XX_INTERNAL_SIZE,
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pflash_table[0], 128 * 1024, 128, 2, 0, 0, 0, 0)) {
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fprintf(stderr, "qemu: Error register flash memory.\n");
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exit(1);
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}
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cpu->env->regs[15] = 0x00000000;
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qemu_irq *irq = qemu_allocate_irqs(connex_smc_irq, cpu, 1);
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smc91c111_init(&nd_table[0], 0x04000300, *irq);
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}
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static void connex_init(int ram_size, int vga_ram_size,
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const char *boot_device, DisplayState *ds,
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const char **fd_filename, int snapshot,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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gumstix_common_init(ram_size, vga_ram_size, ds, kernel_filename,
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kernel_cmdline, initrd_filename, cpu_model, connex);
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}
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QEMUMachine connex_machine = {
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"connex",
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"Gumstix Connex (PXA255)",
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connex_init,
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};
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606
hw/pflash_cfi01.c
Normal file
606
hw/pflash_cfi01.c
Normal file
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@ -0,0 +1,606 @@
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/*
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* CFI parallel flash with Intel command set emulation
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*
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* Copyright (c) 2006 Thorsten Zitterell
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* Copyright (c) 2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/*
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* For now, this code can emulate flashes of 1, 2 or 4 bytes width.
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* Supported commands/modes are:
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* - flash read
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* - flash write
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* - flash ID read
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* - sector erase
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* - CFI queries
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*
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* It does not support timings
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* It does not support flash interleaving
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* It does not implement software data protection as found in many real chips
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* It does not implement erase suspend/resume commands
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* It does not implement multiple sectors erase
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*
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* It does not implement much more ...
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*/
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#include "vl.h"
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#define PFLASH_BUG(fmt, args...) \
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do { \
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printf("PFLASH: Possible BUG - " fmt, ##args); \
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exit(1); \
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} while(0)
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/* #define PFLASH_DEBUG */
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#ifdef PFLASH_DEBUG
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#define DPRINTF(fmt, args...) \
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do { \
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printf("PFLASH: " fmt , ##args); \
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} while (0)
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#else
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#define DPRINTF(fmt, args...) do { } while (0)
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#endif
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struct pflash_t {
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BlockDriverState *bs;
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target_ulong base;
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target_ulong sector_len;
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target_ulong total_len;
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int width;
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int wcycle; /* if 0, the flash is read normally */
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int bypass;
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int ro;
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uint8_t cmd;
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uint8_t status;
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uint16_t ident[4];
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uint8_t cfi_len;
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uint8_t cfi_table[0x52];
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target_ulong counter;
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QEMUTimer *timer;
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ram_addr_t off;
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int fl_mem;
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void *storage;
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};
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static void pflash_timer (void *opaque)
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{
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pflash_t *pfl = opaque;
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DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
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/* Reset flash */
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pfl->status ^= 0x80;
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if (pfl->bypass) {
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pfl->wcycle = 2;
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} else {
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cpu_register_physical_memory(pfl->base, pfl->total_len,
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pfl->off | IO_MEM_ROMD | pfl->fl_mem);
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pfl->wcycle = 0;
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}
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pfl->cmd = 0;
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}
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static uint32_t pflash_read (pflash_t *pfl, target_ulong offset, int width)
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{
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target_ulong boff;
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uint32_t ret;
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uint8_t *p;
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ret = -1;
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offset -= pfl->base;
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boff = offset & 0xFF; /* why this here ?? */
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if (pfl->width == 2)
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boff = boff >> 1;
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else if (pfl->width == 4)
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boff = boff >> 2;
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DPRINTF("%s: reading offset %08x under cmd %02x\n",
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__func__, boff, pfl->cmd);
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switch (pfl->cmd) {
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case 0x00:
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/* Flash area read */
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p = pfl->storage;
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switch (width) {
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case 1:
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ret = p[offset];
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DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
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break;
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case 2:
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#if defined(TARGET_WORDS_BIGENDIAN)
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ret = p[offset] << 8;
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ret |= p[offset + 1];
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#else
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ret = p[offset];
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ret |= p[offset + 1] << 8;
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#endif
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DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
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break;
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case 4:
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#if defined(TARGET_WORDS_BIGENDIAN)
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ret = p[offset] << 24;
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ret |= p[offset + 1] << 16;
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ret |= p[offset + 2] << 8;
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ret |= p[offset + 3];
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#else
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ret = p[offset];
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ret |= p[offset + 1] << 8;
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ret |= p[offset + 1] << 8;
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ret |= p[offset + 2] << 16;
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ret |= p[offset + 3] << 24;
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#endif
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DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
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break;
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default:
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DPRINTF("BUG in %s\n", __func__);
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}
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break;
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case 0x20: /* Block erase */
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case 0x50: /* Clear status register */
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case 0x60: /* Block /un)lock */
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case 0x70: /* Status Register */
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case 0xe8: /* Write block */
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/* Status register read */
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ret = pfl->status;
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DPRINTF("%s: status %x\n", __func__, ret);
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break;
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case 0x98: /* Query mode */
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if (boff > pfl->cfi_len)
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ret = 0;
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else
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ret = pfl->cfi_table[boff];
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break;
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default:
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/* This should never happen : reset state & treat it as a read */
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DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
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pfl->wcycle = 0;
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pfl->cmd = 0;
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}
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return ret;
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}
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/* update flash content on disk */
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static void pflash_update(pflash_t *pfl, int offset,
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int size)
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{
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int offset_end;
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if (pfl->bs) {
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offset_end = offset + size;
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/* round to sectors */
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offset = offset >> 9;
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offset_end = (offset_end + 511) >> 9;
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bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
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offset_end - offset);
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}
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}
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static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
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int width)
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{
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target_ulong boff;
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uint8_t *p;
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uint8_t cmd;
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/* WARNING: when the memory area is in ROMD mode, the offset is a
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ram offset, not a physical address */
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cmd = value;
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if (pfl->wcycle == 0)
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offset -= (target_ulong)(long)pfl->storage;
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else
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offset -= pfl->base;
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DPRINTF("%s: offset %08x %08x %d wcycle 0x%x\n",
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__func__, offset, value, width, pfl->wcycle);
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/* Set the device in I/O access mode */
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cpu_register_physical_memory(pfl->base, pfl->total_len, pfl->fl_mem);
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boff = offset & (pfl->sector_len - 1);
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if (pfl->width == 2)
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boff = boff >> 1;
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else if (pfl->width == 4)
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boff = boff >> 2;
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switch (pfl->wcycle) {
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case 0:
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/* read mode */
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switch (cmd) {
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case 0x00: /* ??? */
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goto reset_flash;
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case 0x20: /* Block erase */
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p = pfl->storage;
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offset &= ~(pfl->sector_len - 1);
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DPRINTF("%s: block erase at 0x%x bytes 0x%x\n", __func__,
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offset, pfl->sector_len);
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memset(p + offset, 0xff, pfl->sector_len);
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pflash_update(pfl, offset, pfl->sector_len);
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pfl->status |= 0x80; /* Ready! */
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break;
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case 0x50: /* Clear status bits */
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DPRINTF("%s: Clear status bits\n", __func__);
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pfl->status = 0x0;
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goto reset_flash;
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case 0x60: /* Block (un)lock */
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DPRINTF("%s: Block unlock\n", __func__);
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break;
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case 0x70: /* Status Register */
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DPRINTF("%s: Read status register\n", __func__);
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pfl->cmd = cmd;
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return;
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case 0x98: /* CFI query */
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DPRINTF("%s: CFI query\n", __func__);
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break;
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case 0xe8: /* Write to buffer */
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DPRINTF("%s: Write to buffer\n", __func__);
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pfl->status |= 0x80; /* Ready! */
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break;
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case 0xff: /* Read array mode */
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DPRINTF("%s: Read array mode\n", __func__);
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goto reset_flash;
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default:
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goto error_flash;
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}
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pfl->wcycle++;
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pfl->cmd = cmd;
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return;
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case 1:
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switch (pfl->cmd) {
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case 0x20: /* Block erase */
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case 0x28:
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if (cmd == 0xd0) { /* confirm */
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pfl->wcycle = 1;
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pfl->status |= 0x80;
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} if (cmd == 0xff) { /* read array mode */
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goto reset_flash;
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} else
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goto error_flash;
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break;
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case 0xe8:
|
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DPRINTF("%s: block write of 0x%x bytes\n", __func__, cmd);
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pfl->counter = cmd;
|
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pfl->wcycle++;
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break;
|
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case 0x60:
|
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if (cmd == 0xd0) {
|
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pfl->wcycle = 0;
|
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pfl->status |= 0x80;
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} else if (cmd == 0x01) {
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pfl->wcycle = 0;
|
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pfl->status |= 0x80;
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} else if (cmd == 0xff) {
|
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goto reset_flash;
|
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} else {
|
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DPRINTF("%s: Unknown (un)locking command\n", __func__);
|
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goto reset_flash;
|
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}
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break;
|
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case 0x98:
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if (cmd == 0xff) {
|
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goto reset_flash;
|
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} else {
|
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DPRINTF("%s: leaving query mode\n", __func__);
|
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}
|
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break;
|
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default:
|
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goto error_flash;
|
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}
|
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return;
|
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case 2:
|
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switch (pfl->cmd) {
|
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case 0xe8: /* Block write */
|
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p = pfl->storage;
|
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DPRINTF("%s: block write offset 0x%x value 0x%x counter 0x%x\n",
|
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__func__, offset, value, pfl->counter);
|
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switch (width) {
|
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case 1:
|
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p[offset] = value;
|
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pflash_update(pfl, offset, 1);
|
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break;
|
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case 2:
|
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#if defined(TARGET_WORDS_BIGENDIAN)
|
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p[offset] = value >> 8;
|
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p[offset + 1] = value;
|
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#else
|
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p[offset] = value;
|
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p[offset + 1] = value >> 8;
|
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#endif
|
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pflash_update(pfl, offset, 2);
|
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break;
|
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case 4:
|
||||
#if defined(TARGET_WORDS_BIGENDIAN)
|
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p[offset] = value >> 24;
|
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p[offset + 1] = value >> 16;
|
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p[offset + 2] = value >> 8;
|
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p[offset + 3] = value;
|
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#else
|
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p[offset] = value;
|
||||
p[offset + 1] = value >> 8;
|
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p[offset + 2] = value >> 16;
|
||||
p[offset + 3] = value >> 24;
|
||||
#endif
|
||||
pflash_update(pfl, offset, 4);
|
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break;
|
||||
}
|
||||
|
||||
pfl->status |= 0x80;
|
||||
|
||||
if (!pfl->counter) {
|
||||
DPRINTF("%s: block write finished\n", __func__);
|
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pfl->wcycle++;
|
||||
}
|
||||
|
||||
pfl->counter--;
|
||||
break;
|
||||
}
|
||||
return;
|
||||
case 3: /* Confirm mode */
|
||||
switch (pfl->cmd) {
|
||||
case 0xe8: /* Block write */
|
||||
if (cmd == 0xd0) {
|
||||
pfl->wcycle = 0;
|
||||
pfl->status |= 0x80;
|
||||
break;
|
||||
} else {
|
||||
DPRINTF("%s: unknown command for \"write block\"\n", __func__);
|
||||
PFLASH_BUG("Write block confirm");
|
||||
}
|
||||
}
|
||||
return;
|
||||
default:
|
||||
/* Should never happen */
|
||||
DPRINTF("%s: invalid write state\n", __func__);
|
||||
goto reset_flash;
|
||||
}
|
||||
return;
|
||||
|
||||
error_flash:
|
||||
printf("%s: Unimplemented flash cmd sequence "
|
||||
"(offset 0x%x, wcycle 0x%x cmd 0x%x value 0x%x\n",
|
||||
__func__, offset, pfl->wcycle, pfl->cmd, value);
|
||||
|
||||
reset_flash:
|
||||
cpu_register_physical_memory(pfl->base, pfl->total_len,
|
||||
pfl->off | IO_MEM_ROMD | pfl->fl_mem);
|
||||
|
||||
pfl->bypass = 0;
|
||||
pfl->wcycle = 0;
|
||||
pfl->cmd = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr)
|
||||
{
|
||||
return pflash_read(opaque, addr, 1);
|
||||
}
|
||||
|
||||
static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr)
|
||||
{
|
||||
pflash_t *pfl = opaque;
|
||||
|
||||
return pflash_read(pfl, addr, 2);
|
||||
}
|
||||
|
||||
static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr)
|
||||
{
|
||||
pflash_t *pfl = opaque;
|
||||
|
||||
return pflash_read(pfl, addr, 4);
|
||||
}
|
||||
|
||||
static void pflash_writeb (void *opaque, target_phys_addr_t addr,
|
||||
uint32_t value)
|
||||
{
|
||||
pflash_write(opaque, addr, value, 1);
|
||||
}
|
||||
|
||||
static void pflash_writew (void *opaque, target_phys_addr_t addr,
|
||||
uint32_t value)
|
||||
{
|
||||
pflash_t *pfl = opaque;
|
||||
|
||||
pflash_write(pfl, addr, value, 2);
|
||||
}
|
||||
|
||||
static void pflash_writel (void *opaque, target_phys_addr_t addr,
|
||||
uint32_t value)
|
||||
{
|
||||
pflash_t *pfl = opaque;
|
||||
|
||||
pflash_write(pfl, addr, value, 4);
|
||||
}
|
||||
|
||||
static CPUWriteMemoryFunc *pflash_write_ops[] = {
|
||||
&pflash_writeb,
|
||||
&pflash_writew,
|
||||
&pflash_writel,
|
||||
};
|
||||
|
||||
static CPUReadMemoryFunc *pflash_read_ops[] = {
|
||||
&pflash_readb,
|
||||
&pflash_readw,
|
||||
&pflash_readl,
|
||||
};
|
||||
|
||||
/* Count trailing zeroes of a 32 bits quantity */
|
||||
static int ctz32 (uint32_t n)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = 0;
|
||||
if (!(n & 0xFFFF)) {
|
||||
ret += 16;
|
||||
n = n >> 16;
|
||||
}
|
||||
if (!(n & 0xFF)) {
|
||||
ret += 8;
|
||||
n = n >> 8;
|
||||
}
|
||||
if (!(n & 0xF)) {
|
||||
ret += 4;
|
||||
n = n >> 4;
|
||||
}
|
||||
if (!(n & 0x3)) {
|
||||
ret += 2;
|
||||
n = n >> 2;
|
||||
}
|
||||
if (!(n & 0x1)) {
|
||||
ret++;
|
||||
n = n >> 1;
|
||||
}
|
||||
#if 0 /* This is not necessary as n is never 0 */
|
||||
if (!n)
|
||||
ret++;
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
|
||||
BlockDriverState *bs,
|
||||
target_ulong sector_len, int nb_blocs, int width,
|
||||
uint16_t id0, uint16_t id1,
|
||||
uint16_t id2, uint16_t id3)
|
||||
{
|
||||
pflash_t *pfl;
|
||||
target_long total_len;
|
||||
|
||||
total_len = sector_len * nb_blocs;
|
||||
|
||||
/* XXX: to be fixed */
|
||||
if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
|
||||
total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
|
||||
return NULL;
|
||||
|
||||
pfl = qemu_mallocz(sizeof(pflash_t));
|
||||
|
||||
if (pfl == NULL)
|
||||
return NULL;
|
||||
pfl->storage = phys_ram_base + off;
|
||||
pfl->fl_mem = cpu_register_io_memory(0,
|
||||
pflash_read_ops, pflash_write_ops, pfl);
|
||||
pfl->off = off;
|
||||
cpu_register_physical_memory(base, total_len,
|
||||
off | pfl->fl_mem | IO_MEM_ROMD);
|
||||
|
||||
pfl->bs = bs;
|
||||
if (pfl->bs) {
|
||||
/* read the initial flash content */
|
||||
bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9);
|
||||
}
|
||||
#if 0 /* XXX: there should be a bit to set up read-only,
|
||||
* the same way the hardware does (with WP pin).
|
||||
*/
|
||||
pfl->ro = 1;
|
||||
#else
|
||||
pfl->ro = 0;
|
||||
#endif
|
||||
pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl);
|
||||
pfl->base = base;
|
||||
pfl->sector_len = sector_len;
|
||||
pfl->total_len = total_len;
|
||||
pfl->width = width;
|
||||
pfl->wcycle = 0;
|
||||
pfl->cmd = 0;
|
||||
pfl->status = 0;
|
||||
pfl->ident[0] = id0;
|
||||
pfl->ident[1] = id1;
|
||||
pfl->ident[2] = id2;
|
||||
pfl->ident[3] = id3;
|
||||
/* Hardcoded CFI table */
|
||||
pfl->cfi_len = 0x52;
|
||||
/* Standard "QRY" string */
|
||||
pfl->cfi_table[0x10] = 'Q';
|
||||
pfl->cfi_table[0x11] = 'R';
|
||||
pfl->cfi_table[0x12] = 'Y';
|
||||
/* Command set (Intel) */
|
||||
pfl->cfi_table[0x13] = 0x01;
|
||||
pfl->cfi_table[0x14] = 0x00;
|
||||
/* Primary extended table address (none) */
|
||||
pfl->cfi_table[0x15] = 0x31;
|
||||
pfl->cfi_table[0x16] = 0x00;
|
||||
/* Alternate command set (none) */
|
||||
pfl->cfi_table[0x17] = 0x00;
|
||||
pfl->cfi_table[0x18] = 0x00;
|
||||
/* Alternate extended table (none) */
|
||||
pfl->cfi_table[0x19] = 0x00;
|
||||
pfl->cfi_table[0x1A] = 0x00;
|
||||
/* Vcc min */
|
||||
pfl->cfi_table[0x1B] = 0x45;
|
||||
/* Vcc max */
|
||||
pfl->cfi_table[0x1C] = 0x55;
|
||||
/* Vpp min (no Vpp pin) */
|
||||
pfl->cfi_table[0x1D] = 0x00;
|
||||
/* Vpp max (no Vpp pin) */
|
||||
pfl->cfi_table[0x1E] = 0x00;
|
||||
/* Reserved */
|
||||
pfl->cfi_table[0x1F] = 0x07;
|
||||
/* Timeout for min size buffer write */
|
||||
pfl->cfi_table[0x20] = 0x07;
|
||||
/* Typical timeout for block erase */
|
||||
pfl->cfi_table[0x21] = 0x0a;
|
||||
/* Typical timeout for full chip erase (4096 ms) */
|
||||
pfl->cfi_table[0x22] = 0x00;
|
||||
/* Reserved */
|
||||
pfl->cfi_table[0x23] = 0x04;
|
||||
/* Max timeout for buffer write */
|
||||
pfl->cfi_table[0x24] = 0x04;
|
||||
/* Max timeout for block erase */
|
||||
pfl->cfi_table[0x25] = 0x04;
|
||||
/* Max timeout for chip erase */
|
||||
pfl->cfi_table[0x26] = 0x00;
|
||||
/* Device size */
|
||||
pfl->cfi_table[0x27] = ctz32(total_len); // + 1;
|
||||
/* Flash device interface (8 & 16 bits) */
|
||||
pfl->cfi_table[0x28] = 0x02;
|
||||
pfl->cfi_table[0x29] = 0x00;
|
||||
/* Max number of bytes in multi-bytes write */
|
||||
pfl->cfi_table[0x2A] = 0x04;
|
||||
pfl->cfi_table[0x2B] = 0x00;
|
||||
/* Number of erase block regions (uniform) */
|
||||
pfl->cfi_table[0x2C] = 0x01;
|
||||
/* Erase block region 1 */
|
||||
pfl->cfi_table[0x2D] = nb_blocs - 1;
|
||||
pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8;
|
||||
pfl->cfi_table[0x2F] = sector_len >> 8;
|
||||
pfl->cfi_table[0x30] = sector_len >> 16;
|
||||
|
||||
/* Extended */
|
||||
pfl->cfi_table[0x31] = 'P';
|
||||
pfl->cfi_table[0x32] = 'R';
|
||||
pfl->cfi_table[0x33] = 'I';
|
||||
|
||||
pfl->cfi_table[0x34] = '1';
|
||||
pfl->cfi_table[0x35] = '1';
|
||||
|
||||
pfl->cfi_table[0x36] = 0x00;
|
||||
pfl->cfi_table[0x37] = 0x00;
|
||||
pfl->cfi_table[0x38] = 0x00;
|
||||
pfl->cfi_table[0x39] = 0x00;
|
||||
|
||||
pfl->cfi_table[0x3a] = 0x00;
|
||||
|
||||
pfl->cfi_table[0x3b] = 0x00;
|
||||
pfl->cfi_table[0x3c] = 0x00;
|
||||
|
||||
return pfl;
|
||||
}
|
4
vl.c
4
vl.c
|
@ -7435,6 +7435,7 @@ void register_machines(void)
|
|||
qemu_register_machine(&palmte_machine);
|
||||
qemu_register_machine(&lm3s811evb_machine);
|
||||
qemu_register_machine(&lm3s6965evb_machine);
|
||||
qemu_register_machine(&connex_machine);
|
||||
#elif defined(TARGET_SH4)
|
||||
qemu_register_machine(&shix_machine);
|
||||
qemu_register_machine(&r2d_machine);
|
||||
|
@ -8260,7 +8261,8 @@ int main(int argc, char **argv)
|
|||
if (!linux_boot && net_boot == 0 &&
|
||||
hd_filename[0] == '\0' &&
|
||||
(cdrom_index >= 0 && hd_filename[cdrom_index] == '\0') &&
|
||||
fd_filename[0] == '\0')
|
||||
fd_filename[0] == '\0' &&
|
||||
pflash_filename[0] == '\0')
|
||||
help(1);
|
||||
|
||||
/* boot to floppy or the default cd if no hard disk defined yet */
|
||||
|
|
Loading…
Reference in a new issue