target/ppc: merge ppc_vsr_t and ppc_avr_t union types
Since the VSX registers are actually a superset of the VMX registers then they can be represented by the same type. Merge ppc_avr_t into ppc_vsr_t and change ppc_avr_t to be a simple typedef alias. Note that due to a difference in the naming of the float32 member between ppc_avr_t and ppc_vsr_t, references to the ppc_avr_t f member must be replaced with f32 instead. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -218,7 +218,6 @@ typedef struct opc_handler_t opc_handler_t;
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/* Types used to describe some PowerPC registers etc. */
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typedef struct DisasContext DisasContext;
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typedef struct ppc_spr_t ppc_spr_t;
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typedef union ppc_avr_t ppc_avr_t;
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typedef union ppc_tlb_t ppc_tlb_t;
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typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
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@ -242,22 +241,26 @@ struct ppc_spr_t {
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#endif
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};
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/* Altivec registers (128 bits) */
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union ppc_avr_t {
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float32 f[4];
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/* VSX/Altivec registers (128 bits) */
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typedef union _ppc_vsr_t {
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uint8_t u8[16];
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uint16_t u16[8];
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uint32_t u32[4];
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uint64_t u64[2];
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int8_t s8[16];
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int16_t s16[8];
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int32_t s32[4];
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uint64_t u64[2];
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int64_t s64[2];
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float32 f32[4];
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float64 f64[2];
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float128 f128;
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#ifdef CONFIG_INT128
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__uint128_t u128;
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#endif
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Int128 s128;
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};
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Int128 s128;
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} ppc_vsr_t;
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typedef ppc_vsr_t ppc_avr_t;
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#if !defined(CONFIG_USER_ONLY)
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/* Software TLB cache */
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@ -548,8 +548,8 @@ VARITH_DO(muluwm, *, u32)
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{ \
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int i; \
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\
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for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
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r->f[i] = func(a->f[i], b->f[i], &env->vec_status); \
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for (i = 0; i < ARRAY_SIZE(r->f32); i++) { \
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r->f32[i] = func(a->f32[i], b->f32[i], &env->vec_status); \
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} \
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}
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VARITHFP(addfp, float32_add)
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@ -563,9 +563,9 @@ VARITHFP(maxfp, float32_max)
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ppc_avr_t *b, ppc_avr_t *c) \
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{ \
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int i; \
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for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
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r->f[i] = float32_muladd(a->f[i], c->f[i], b->f[i], \
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type, &env->vec_status); \
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for (i = 0; i < ARRAY_SIZE(r->f32); i++) { \
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r->f32[i] = float32_muladd(a->f32[i], c->f32[i], b->f32[i], \
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type, &env->vec_status); \
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} \
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}
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VARITHFPFMA(maddfp, 0);
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@ -670,9 +670,9 @@ VABSDU(w, u32)
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{ \
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int i; \
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\
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for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
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for (i = 0; i < ARRAY_SIZE(r->f32); i++) { \
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float32 t = cvt(b->element[i], &env->vec_status); \
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r->f[i] = float32_scalbn(t, -uim, &env->vec_status); \
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r->f32[i] = float32_scalbn(t, -uim, &env->vec_status); \
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} \
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}
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VCF(ux, uint32_to_float32, u32)
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@ -782,9 +782,9 @@ VCMPNE(w, u32, uint32_t, 0)
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uint32_t none = 0; \
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int i; \
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\
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for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
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for (i = 0; i < ARRAY_SIZE(r->f32); i++) { \
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uint32_t result; \
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int rel = float32_compare_quiet(a->f[i], b->f[i], \
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int rel = float32_compare_quiet(a->f32[i], b->f32[i], \
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&env->vec_status); \
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if (rel == float_relation_unordered) { \
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result = 0; \
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@ -816,14 +816,16 @@ static inline void vcmpbfp_internal(CPUPPCState *env, ppc_avr_t *r,
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int i;
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int all_in = 0;
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for (i = 0; i < ARRAY_SIZE(r->f); i++) {
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int le_rel = float32_compare_quiet(a->f[i], b->f[i], &env->vec_status);
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for (i = 0; i < ARRAY_SIZE(r->f32); i++) {
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int le_rel = float32_compare_quiet(a->f32[i], b->f32[i],
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&env->vec_status);
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if (le_rel == float_relation_unordered) {
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r->u32[i] = 0xc0000000;
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all_in = 1;
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} else {
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float32 bneg = float32_chs(b->f[i]);
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int ge_rel = float32_compare_quiet(a->f[i], bneg, &env->vec_status);
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float32 bneg = float32_chs(b->f32[i]);
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int ge_rel = float32_compare_quiet(a->f32[i], bneg,
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&env->vec_status);
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int le = le_rel != float_relation_greater;
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int ge = ge_rel != float_relation_less;
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@ -856,11 +858,11 @@ void helper_vcmpbfp_dot(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a,
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float_status s = env->vec_status; \
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\
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set_float_rounding_mode(float_round_to_zero, &s); \
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for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
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if (float32_is_any_nan(b->f[i])) { \
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for (i = 0; i < ARRAY_SIZE(r->f32); i++) { \
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if (float32_is_any_nan(b->f32[i])) { \
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r->element[i] = 0; \
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} else { \
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float64 t = float32_to_float64(b->f[i], &s); \
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float64 t = float32_to_float64(b->f32[i], &s); \
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int64_t j; \
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\
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t = float64_scalbn(t, uim, &s); \
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@ -1661,8 +1663,8 @@ void helper_vrefp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *b)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(r->f); i++) {
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r->f[i] = float32_div(float32_one, b->f[i], &env->vec_status);
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for (i = 0; i < ARRAY_SIZE(r->f32); i++) {
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r->f32[i] = float32_div(float32_one, b->f32[i], &env->vec_status);
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}
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}
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@ -1674,8 +1676,8 @@ void helper_vrefp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *b)
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float_status s = env->vec_status; \
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\
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set_float_rounding_mode(rounding, &s); \
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for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
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r->f[i] = float32_round_to_int (b->f[i], &s); \
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for (i = 0; i < ARRAY_SIZE(r->f32); i++) { \
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r->f32[i] = float32_round_to_int (b->f32[i], &s); \
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} \
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}
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VRFI(n, float_round_nearest_even)
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@ -1705,10 +1707,10 @@ void helper_vrsqrtefp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *b)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(r->f); i++) {
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float32 t = float32_sqrt(b->f[i], &env->vec_status);
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for (i = 0; i < ARRAY_SIZE(r->f32); i++) {
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float32 t = float32_sqrt(b->f32[i], &env->vec_status);
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r->f[i] = float32_div(float32_one, t, &env->vec_status);
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r->f32[i] = float32_div(float32_one, t, &env->vec_status);
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}
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}
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@ -1751,8 +1753,8 @@ void helper_vexptefp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *b)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(r->f); i++) {
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r->f[i] = float32_exp2(b->f[i], &env->vec_status);
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for (i = 0; i < ARRAY_SIZE(r->f32); i++) {
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r->f32[i] = float32_exp2(b->f32[i], &env->vec_status);
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}
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}
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@ -1760,8 +1762,8 @@ void helper_vlogefp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *b)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(r->f); i++) {
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r->f[i] = float32_log2(b->f[i], &env->vec_status);
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for (i = 0; i < ARRAY_SIZE(r->f32); i++) {
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r->f32[i] = float32_log2(b->f32[i], &env->vec_status);
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}
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}
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@ -204,17 +204,6 @@ EXTRACT_HELPER(IMM8, 11, 8);
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EXTRACT_HELPER(DCMX, 16, 7);
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EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1, 6, 6);
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typedef union _ppc_vsr_t {
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uint8_t u8[16];
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uint16_t u16[8];
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uint32_t u32[4];
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uint64_t u64[2];
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float32 f32[4];
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float64 f64[2];
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float128 f128;
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Int128 s128;
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} ppc_vsr_t;
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#if defined(HOST_WORDS_BIGENDIAN)
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#define VsrB(i) u8[i]
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#define VsrH(i) u16[i]
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