hw/openpic.c: replace tabs by spaces
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno
parent
b4b784fe98
commit
060fbfe1d6
262
hw/openpic.c
262
hw/openpic.c
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@ -219,20 +219,20 @@ typedef struct openpic_t {
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int nb_cpus;
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/* Timer registers */
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struct {
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uint32_t ticc; /* Global timer current count register */
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uint32_t tibc; /* Global timer base count register */
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uint32_t ticc; /* Global timer current count register */
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uint32_t tibc; /* Global timer base count register */
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} timers[MAX_TMR];
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#if MAX_DBL > 0
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/* Doorbell registers */
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uint32_t dar; /* Doorbell activate register */
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struct {
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uint32_t dmr; /* Doorbell messaging register */
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uint32_t dmr; /* Doorbell messaging register */
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} doorbells[MAX_DBL];
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#endif
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#if MAX_MBX > 0
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/* Mailbox registers */
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struct {
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uint32_t mbr; /* Mailbox register */
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uint32_t mbr; /* Mailbox register */
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} mailboxes[MAX_MAILBOXES];
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#endif
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/* IRQ out is used when in bypass mode (not implemented) */
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@ -276,14 +276,14 @@ static void IRQ_check (openpic_t *opp, IRQ_queue_t *q)
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next = -1;
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priority = -1;
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for (i = 0; i < opp->max_irq; i++) {
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if (IRQ_testbit(q, i)) {
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if (IRQ_testbit(q, i)) {
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DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n",
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i, IPVP_PRIORITY(opp->src[i].ipvp), priority);
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if (IPVP_PRIORITY(opp->src[i].ipvp) > priority) {
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next = i;
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priority = IPVP_PRIORITY(opp->src[i].ipvp);
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}
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}
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if (IPVP_PRIORITY(opp->src[i].ipvp) > priority) {
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next = i;
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priority = IPVP_PRIORITY(opp->src[i].ipvp);
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}
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}
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}
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q->next = next;
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q->priority = priority;
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@ -293,7 +293,7 @@ static int IRQ_get_next (openpic_t *opp, IRQ_queue_t *q)
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{
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if (q->next == -1) {
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/* XXX: optimize */
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IRQ_check(opp, q);
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IRQ_check(opp, q);
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}
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return q->next;
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@ -309,16 +309,16 @@ static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ)
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src = &opp->src[n_IRQ];
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priority = IPVP_PRIORITY(src->ipvp);
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if (priority <= dst->pctp) {
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/* Too low priority */
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/* Too low priority */
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DPRINTF("%s: IRQ %d has too low priority on CPU %d\n",
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__func__, n_IRQ, n_CPU);
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return;
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return;
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}
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if (IRQ_testbit(&dst->raised, n_IRQ)) {
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/* Interrupt miss */
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/* Interrupt miss */
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DPRINTF("%s: IRQ %d was missed on CPU %d\n",
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__func__, n_IRQ, n_CPU);
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return;
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return;
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}
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set_bit(&src->ipvp, IPVP_ACTIVITY);
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IRQ_setbit(&dst->raised, n_IRQ);
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@ -354,14 +354,14 @@ static void openpic_update_irq(openpic_t *opp, int n_IRQ)
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return;
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}
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if (test_bit(&src->ipvp, IPVP_MASK)) {
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/* Interrupt source is disabled */
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/* Interrupt source is disabled */
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DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ);
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return;
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return;
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}
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if (IPVP_PRIORITY(src->ipvp) == 0) {
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/* Priority set to zero */
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/* Priority set to zero */
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DPRINTF("%s: IRQ %d has 0 priority\n", __func__, n_IRQ);
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return;
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return;
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}
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if (test_bit(&src->ipvp, IPVP_ACTIVITY)) {
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/* IRQ already active */
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@ -369,9 +369,9 @@ static void openpic_update_irq(openpic_t *opp, int n_IRQ)
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return;
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}
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if (src->ide == 0x00000000) {
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/* No target */
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/* No target */
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DPRINTF("%s: IRQ %d has no target\n", __func__, n_IRQ);
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return;
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return;
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}
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if (src->ide == (1 << src->last_cpu)) {
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@ -434,34 +434,34 @@ static void openpic_reset (void *opaque)
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opp->micr = 0x00000000;
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/* Initialise IRQ sources */
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for (i = 0; i < opp->max_irq; i++) {
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opp->src[i].ipvp = 0xA0000000;
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opp->src[i].ide = 0x00000000;
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opp->src[i].ipvp = 0xA0000000;
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opp->src[i].ide = 0x00000000;
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}
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/* Initialise IRQ destinations */
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for (i = 0; i < MAX_CPU; i++) {
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opp->dst[i].pctp = 0x0000000F;
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opp->dst[i].pcsr = 0x00000000;
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memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t));
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opp->dst[i].pctp = 0x0000000F;
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opp->dst[i].pcsr = 0x00000000;
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memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t));
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opp->dst[i].raised.next = -1;
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memset(&opp->dst[i].servicing, 0, sizeof(IRQ_queue_t));
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memset(&opp->dst[i].servicing, 0, sizeof(IRQ_queue_t));
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opp->dst[i].servicing.next = -1;
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}
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/* Initialise timers */
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for (i = 0; i < MAX_TMR; i++) {
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opp->timers[i].ticc = 0x00000000;
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opp->timers[i].tibc = 0x80000000;
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opp->timers[i].ticc = 0x00000000;
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opp->timers[i].tibc = 0x80000000;
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}
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/* Initialise doorbells */
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#if MAX_DBL > 0
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opp->dar = 0x00000000;
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for (i = 0; i < MAX_DBL; i++) {
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opp->doorbells[i].dmr = 0x00000000;
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opp->doorbells[i].dmr = 0x00000000;
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}
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#endif
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/* Initialise mailboxes */
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#if MAX_MBX > 0
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for (i = 0; i < MAX_MBX; i++) { /* ? */
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opp->mailboxes[i].mbr = 0x00000000;
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opp->mailboxes[i].mbr = 0x00000000;
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}
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#endif
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/* Go out of RESET state */
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@ -474,11 +474,11 @@ static inline uint32_t read_IRQreg (openpic_t *opp, int n_IRQ, uint32_t reg)
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switch (reg) {
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case IRQ_IPVP:
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retval = opp->src[n_IRQ].ipvp;
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break;
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retval = opp->src[n_IRQ].ipvp;
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break;
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case IRQ_IDE:
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retval = opp->src[n_IRQ].ide;
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break;
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retval = opp->src[n_IRQ].ide;
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break;
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}
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return retval;
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@ -494,95 +494,95 @@ static inline void write_IRQreg (openpic_t *opp, int n_IRQ,
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/* NOTE: not fully accurate for special IRQs, but simple and
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sufficient */
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/* ACTIVITY bit is read-only */
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opp->src[n_IRQ].ipvp =
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opp->src[n_IRQ].ipvp =
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(opp->src[n_IRQ].ipvp & 0x40000000) |
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(val & 0x800F00FF);
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openpic_update_irq(opp, n_IRQ);
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DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n",
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n_IRQ, val, opp->src[n_IRQ].ipvp);
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break;
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break;
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case IRQ_IDE:
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tmp = val & 0xC0000000;
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tmp = val & 0xC0000000;
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tmp |= val & ((1 << MAX_CPU) - 1);
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opp->src[n_IRQ].ide = tmp;
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opp->src[n_IRQ].ide = tmp;
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DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide);
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break;
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break;
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}
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}
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#if 0 // Code provision for Intel model
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#if MAX_DBL > 0
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static uint32_t read_doorbell_register (openpic_t *opp,
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int n_dbl, uint32_t offset)
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int n_dbl, uint32_t offset)
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{
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uint32_t retval;
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switch (offset) {
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case DBL_IPVP_OFFSET:
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retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP);
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break;
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retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP);
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break;
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case DBL_IDE_OFFSET:
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retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE);
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break;
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retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE);
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break;
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case DBL_DMR_OFFSET:
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retval = opp->doorbells[n_dbl].dmr;
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break;
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retval = opp->doorbells[n_dbl].dmr;
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break;
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}
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return retval;
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}
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static void write_doorbell_register (penpic_t *opp, int n_dbl,
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uint32_t offset, uint32_t value)
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uint32_t offset, uint32_t value)
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{
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switch (offset) {
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case DBL_IVPR_OFFSET:
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write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP, value);
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break;
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write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP, value);
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break;
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case DBL_IDE_OFFSET:
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write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE, value);
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break;
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write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE, value);
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break;
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case DBL_DMR_OFFSET:
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opp->doorbells[n_dbl].dmr = value;
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break;
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opp->doorbells[n_dbl].dmr = value;
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break;
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}
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}
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#endif
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#if MAX_MBX > 0
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static uint32_t read_mailbox_register (openpic_t *opp,
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int n_mbx, uint32_t offset)
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int n_mbx, uint32_t offset)
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{
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uint32_t retval;
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switch (offset) {
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case MBX_MBR_OFFSET:
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retval = opp->mailboxes[n_mbx].mbr;
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break;
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retval = opp->mailboxes[n_mbx].mbr;
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break;
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case MBX_IVPR_OFFSET:
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retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP);
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break;
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retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP);
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break;
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case MBX_DMR_OFFSET:
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retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE);
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break;
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retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE);
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break;
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}
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return retval;
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}
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static void write_mailbox_register (openpic_t *opp, int n_mbx,
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uint32_t address, uint32_t value)
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uint32_t address, uint32_t value)
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{
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switch (offset) {
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case MBX_MBR_OFFSET:
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opp->mailboxes[n_mbx].mbr = value;
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break;
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opp->mailboxes[n_mbx].mbr = value;
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break;
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case MBX_IVPR_OFFSET:
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write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP, value);
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break;
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write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP, value);
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break;
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case MBX_DMR_OFFSET:
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write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE, value);
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break;
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write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE, value);
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break;
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}
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}
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#endif
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@ -608,9 +608,9 @@ static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t v
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if (val & 0x80000000 && opp->reset)
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opp->reset(opp);
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opp->glbc = val & ~0x80000000;
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break;
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break;
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case 0x80: /* VENI */
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break;
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break;
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case 0x90: /* PINT */
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for (idx = 0; idx < opp->nb_cpus; idx++) {
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if ((val & (1 << idx)) && !(opp->pint & (1 << idx))) {
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@ -624,7 +624,7 @@ static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t v
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}
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}
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opp->pint = val;
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break;
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break;
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#if MAX_IPI > 0
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case 0xA0: /* IPI_IPVP */
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case 0xB0:
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@ -642,7 +642,7 @@ static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t v
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break;
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case 0xF0: /* TIFR */
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opp->tifr = val;
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break;
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break;
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default:
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break;
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}
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@ -664,13 +664,13 @@ static uint32_t openpic_gbl_read (void *opaque, target_phys_addr_t addr)
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break;
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case 0x20: /* GLBC */
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retval = opp->glbc;
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break;
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break;
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case 0x80: /* VENI */
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retval = opp->veni;
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break;
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break;
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case 0x90: /* PINT */
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retval = 0x00000000;
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break;
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break;
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#if MAX_IPI > 0
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case 0xA0: /* IPI_IPVP */
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case 0xB0:
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@ -681,14 +681,14 @@ static uint32_t openpic_gbl_read (void *opaque, target_phys_addr_t addr)
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idx = (addr - 0xA0) >> 4;
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retval = read_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IPVP);
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}
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break;
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break;
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#endif
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case 0xE0: /* SPVE */
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retval = opp->spve;
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break;
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case 0xF0: /* TIFR */
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retval = opp->tifr;
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break;
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break;
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default:
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break;
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}
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@ -719,18 +719,18 @@ static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val)
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case 0x00: /* TICC */
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break;
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case 0x10: /* TIBC */
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if ((opp->timers[idx].ticc & 0x80000000) != 0 &&
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(val & 0x80000000) == 0 &&
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if ((opp->timers[idx].ticc & 0x80000000) != 0 &&
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(val & 0x80000000) == 0 &&
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(opp->timers[idx].tibc & 0x80000000) != 0)
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opp->timers[idx].ticc &= ~0x80000000;
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opp->timers[idx].tibc = val;
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break;
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opp->timers[idx].ticc &= ~0x80000000;
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opp->timers[idx].tibc = val;
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break;
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case 0x20: /* TIVP */
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write_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IPVP, val);
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break;
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break;
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case 0x30: /* TIDE */
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write_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IDE, val);
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break;
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break;
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}
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}
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@ -750,17 +750,17 @@ static uint32_t openpic_timer_read (void *opaque, uint32_t addr)
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addr = addr & 0x30;
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switch (addr) {
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case 0x00: /* TICC */
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retval = opp->timers[idx].ticc;
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retval = opp->timers[idx].ticc;
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break;
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case 0x10: /* TIBC */
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retval = opp->timers[idx].tibc;
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break;
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retval = opp->timers[idx].tibc;
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break;
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case 0x20: /* TIPV */
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retval = read_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IPVP);
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break;
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break;
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case 0x30: /* TIDE */
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retval = read_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IDE);
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break;
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break;
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}
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DPRINTF("%s: => %08x\n", __func__, retval);
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#if defined TARGET_WORDS_BIGENDIAN
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@ -849,21 +849,21 @@ static void openpic_cpu_write (void *opaque, target_phys_addr_t addr, uint32_t v
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break;
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#endif
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case 0x80: /* PCTP */
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dst->pctp = val & 0x0000000F;
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break;
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dst->pctp = val & 0x0000000F;
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break;
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case 0x90: /* WHOAMI */
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/* Read-only register */
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break;
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/* Read-only register */
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break;
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case 0xA0: /* PIAC */
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/* Read-only register */
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break;
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/* Read-only register */
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break;
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case 0xB0: /* PEOI */
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DPRINTF("PEOI\n");
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s_IRQ = IRQ_get_next(opp, &dst->servicing);
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IRQ_resetbit(&dst->servicing, s_IRQ);
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dst->servicing.next = -1;
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||||
/* Set up next servicing IRQ */
|
||||
s_IRQ = IRQ_get_next(opp, &dst->servicing);
|
||||
s_IRQ = IRQ_get_next(opp, &dst->servicing);
|
||||
IRQ_resetbit(&dst->servicing, s_IRQ);
|
||||
dst->servicing.next = -1;
|
||||
/* Set up next servicing IRQ */
|
||||
s_IRQ = IRQ_get_next(opp, &dst->servicing);
|
||||
/* Check queued interrupts. */
|
||||
n_IRQ = IRQ_get_next(opp, &dst->raised);
|
||||
src = &opp->src[n_IRQ];
|
||||
|
|
@ -874,7 +874,7 @@ static void openpic_cpu_write (void *opaque, target_phys_addr_t addr, uint32_t v
|
|||
idx, n_IRQ);
|
||||
opp->irq_raise(opp, idx, src);
|
||||
}
|
||||
break;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
@ -898,46 +898,46 @@ static uint32_t openpic_cpu_read (void *opaque, target_phys_addr_t addr)
|
|||
addr &= 0xFF0;
|
||||
switch (addr) {
|
||||
case 0x80: /* PCTP */
|
||||
retval = dst->pctp;
|
||||
break;
|
||||
retval = dst->pctp;
|
||||
break;
|
||||
case 0x90: /* WHOAMI */
|
||||
retval = idx;
|
||||
break;
|
||||
retval = idx;
|
||||
break;
|
||||
case 0xA0: /* PIAC */
|
||||
DPRINTF("Lower OpenPIC INT output\n");
|
||||
qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]);
|
||||
n_IRQ = IRQ_get_next(opp, &dst->raised);
|
||||
n_IRQ = IRQ_get_next(opp, &dst->raised);
|
||||
DPRINTF("PIAC: irq=%d\n", n_IRQ);
|
||||
if (n_IRQ == -1) {
|
||||
/* No more interrupt pending */
|
||||
if (n_IRQ == -1) {
|
||||
/* No more interrupt pending */
|
||||
retval = IPVP_VECTOR(opp->spve);
|
||||
} else {
|
||||
src = &opp->src[n_IRQ];
|
||||
if (!test_bit(&src->ipvp, IPVP_ACTIVITY) ||
|
||||
!(IPVP_PRIORITY(src->ipvp) > dst->pctp)) {
|
||||
/* - Spurious level-sensitive IRQ
|
||||
* - Priorities has been changed
|
||||
* and the pending IRQ isn't allowed anymore
|
||||
*/
|
||||
reset_bit(&src->ipvp, IPVP_ACTIVITY);
|
||||
retval = IPVP_VECTOR(opp->spve);
|
||||
} else {
|
||||
/* IRQ enter servicing state */
|
||||
IRQ_setbit(&dst->servicing, n_IRQ);
|
||||
retval = IPVP_VECTOR(src->ipvp);
|
||||
}
|
||||
IRQ_resetbit(&dst->raised, n_IRQ);
|
||||
dst->raised.next = -1;
|
||||
if (!test_bit(&src->ipvp, IPVP_SENSE)) {
|
||||
} else {
|
||||
src = &opp->src[n_IRQ];
|
||||
if (!test_bit(&src->ipvp, IPVP_ACTIVITY) ||
|
||||
!(IPVP_PRIORITY(src->ipvp) > dst->pctp)) {
|
||||
/* - Spurious level-sensitive IRQ
|
||||
* - Priorities has been changed
|
||||
* and the pending IRQ isn't allowed anymore
|
||||
*/
|
||||
reset_bit(&src->ipvp, IPVP_ACTIVITY);
|
||||
retval = IPVP_VECTOR(opp->spve);
|
||||
} else {
|
||||
/* IRQ enter servicing state */
|
||||
IRQ_setbit(&dst->servicing, n_IRQ);
|
||||
retval = IPVP_VECTOR(src->ipvp);
|
||||
}
|
||||
IRQ_resetbit(&dst->raised, n_IRQ);
|
||||
dst->raised.next = -1;
|
||||
if (!test_bit(&src->ipvp, IPVP_SENSE)) {
|
||||
/* edge-sensitive IRQ */
|
||||
reset_bit(&src->ipvp, IPVP_ACTIVITY);
|
||||
reset_bit(&src->ipvp, IPVP_ACTIVITY);
|
||||
src->pending = 0;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 0xB0: /* PEOI */
|
||||
retval = 0;
|
||||
break;
|
||||
retval = 0;
|
||||
break;
|
||||
#if MAX_IPI > 0
|
||||
case 0x40: /* IDE */
|
||||
case 0x50:
|
||||
|
|
|
|||
Loading…
Reference in a new issue