ICH9: fix typo
Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
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@ -97,8 +97,8 @@ static void ich9_cc_update(ICH9LPCState *lpc)
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/*
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/*
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* D30: DMI2PCI bridge
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* D30: DMI2PCI bridge
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* It is arbitrarily decided how INTx lines of PCI devicesbehind the bridge
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* It is arbitrarily decided how INTx lines of PCI devices behind
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* are connected to pirq lines. Our choice is PIRQ[E-H].
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* the bridge are connected to pirq lines. Our choice is PIRQ[E-H].
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* INT[A-D] are connected to PIRQ[E-H]
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* INT[A-D] are connected to PIRQ[E-H]
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*/
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*/
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for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) {
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for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) {
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@ -35,7 +35,7 @@ typedef struct ICH9LPCState {
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/* (pci device, intx) -> pirq
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/* (pci device, intx) -> pirq
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* In real chipset case, the unused slots are never used
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* In real chipset case, the unused slots are never used
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* as ICH9 supports only D25-D32 irq routing.
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* as ICH9 supports only D25-D31 irq routing.
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* On the other hand in qemu case, any slot/function can be populated
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* On the other hand in qemu case, any slot/function can be populated
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* via command line option.
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* via command line option.
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* So fallback interrupt routing for any devices in any slots is necessary.
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* So fallback interrupt routing for any devices in any slots is necessary.
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@ -181,7 +181,7 @@ Object *ich9_lpc_find(void);
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#define ICH9_SATA1_DEV 31
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#define ICH9_SATA1_DEV 31
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#define ICH9_SATA1_FUNC 2
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#define ICH9_SATA1_FUNC 2
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/* D30:F1 power management I/O registers
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/* D31:F0 power management I/O registers
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offset from the address ICH9_LPC_PMBASE */
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offset from the address ICH9_LPC_PMBASE */
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/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
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/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
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