ppc/pnv: Use address_space_stq_be() when triggering an interrupt from PSI
Include the XIVE_TRIGGER_PQ bit in the trigger data which is how hardware signals to the IC that the PQ bits of the interrupt source have been checked. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191007084102.29776-3-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -660,10 +660,19 @@ static void pnv_psi_notify(XiveNotifier *xf, uint32_t srcno)
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uint32_t offset =
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(psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT);
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uint64_t lisn = cpu_to_be64(offset + srcno);
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uint64_t data = XIVE_TRIGGER_PQ | offset | srcno;
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MemTxResult result;
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if (valid) {
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cpu_physical_memory_write(notify_addr, &lisn, sizeof(lisn));
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if (!valid) {
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return;
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}
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address_space_stq_be(&address_space_memory, notify_addr, data,
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MEMTXATTRS_UNSPECIFIED, &result);
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if (result != MEMTX_OK) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: trigger failed @%"
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HWADDR_PRIx "\n", __func__, notif_port);
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return;
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}
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}
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