target-tricore: Add instructions of SRC opcode format
Add instructions of SRC opcode format. Add micro-op generator functions for add, conditional add/sub and shi/shai. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1409572800-4116-7-git-send-email-kbastian@mail.uni-paderborn.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Bastian Koppelmann
Peter Maydell
parent
7c87d074d2
commit
0707ec1bea
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@ -0,0 +1,16 @@
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/*
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* Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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@ -27,6 +27,7 @@
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#include "exec/helper-gen.h"
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#include "tricore-opcodes.h"
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/*
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* TCG registers
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*/
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@ -102,8 +103,258 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f,
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}
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/*
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* Functions to generate micro-ops
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*/
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/* Functions for arithmetic instructions */
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static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
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{
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TCGv t0 = tcg_temp_new_i32();
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TCGv result = tcg_temp_new_i32();
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/* Addition and set V/SV bits */
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tcg_gen_add_tl(result, r1, r2);
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/* calc V bit */
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tcg_gen_xor_tl(cpu_PSW_V, result, r1);
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tcg_gen_xor_tl(t0, r1, r2);
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tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
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/* Calc SV bit */
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tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
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/* Calc AV/SAV bits */
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tcg_gen_add_tl(cpu_PSW_AV, result, result);
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tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
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/* calc SAV */
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tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
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/* write back result */
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tcg_gen_mov_tl(ret, result);
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tcg_temp_free(result);
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tcg_temp_free(t0);
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}
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static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2)
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{
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TCGv temp = tcg_const_i32(r2);
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gen_add_d(ret, r1, temp);
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tcg_temp_free(temp);
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}
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static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
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TCGv r4)
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{
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TCGv temp = tcg_temp_new();
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TCGv temp2 = tcg_temp_new();
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TCGv result = tcg_temp_new();
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TCGv mask = tcg_temp_new();
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TCGv t0 = tcg_const_i32(0);
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/* create mask for sticky bits */
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tcg_gen_setcond_tl(cond, mask, r4, t0);
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tcg_gen_shli_tl(mask, mask, 31);
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tcg_gen_add_tl(result, r1, r2);
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/* Calc PSW_V */
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tcg_gen_xor_tl(temp, result, r1);
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tcg_gen_xor_tl(temp2, r1, r2);
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tcg_gen_andc_tl(temp, temp, temp2);
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tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
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/* Set PSW_SV */
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tcg_gen_and_tl(temp, temp, mask);
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tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
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/* calc AV bit */
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tcg_gen_add_tl(temp, result, result);
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tcg_gen_xor_tl(temp, temp, result);
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tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
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/* calc SAV bit */
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tcg_gen_and_tl(temp, temp, mask);
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tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
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/* write back result */
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tcg_gen_movcond_tl(cond, r3, r4, t0, result, r3);
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tcg_temp_free(t0);
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tcg_temp_free(temp);
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tcg_temp_free(temp2);
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tcg_temp_free(result);
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tcg_temp_free(mask);
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}
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static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2,
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TCGv r3, TCGv r4)
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{
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TCGv temp = tcg_const_i32(r2);
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gen_cond_add(cond, r1, temp, r3, r4);
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tcg_temp_free(temp);
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}
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static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
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{
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if (shift_count == -32) {
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tcg_gen_movi_tl(ret, 0);
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} else if (shift_count >= 0) {
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tcg_gen_shli_tl(ret, r1, shift_count);
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} else {
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tcg_gen_shri_tl(ret, r1, -shift_count);
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}
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}
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static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
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{
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uint32_t msk, msk_start;
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TCGv temp = tcg_temp_new();
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TCGv temp2 = tcg_temp_new();
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TCGv t_0 = tcg_const_i32(0);
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if (shift_count == 0) {
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/* Clear PSW.C and PSW.V */
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tcg_gen_movi_tl(cpu_PSW_C, 0);
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tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C);
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tcg_gen_mov_tl(ret, r1);
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} else if (shift_count == -32) {
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/* set PSW.C */
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tcg_gen_mov_tl(cpu_PSW_C, r1);
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/* fill ret completly with sign bit */
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tcg_gen_sari_tl(ret, r1, 31);
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/* clear PSW.V */
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tcg_gen_movi_tl(cpu_PSW_V, 0);
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} else if (shift_count > 0) {
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TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count);
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TCGv t_min = tcg_const_i32(((int32_t) -0x80000000) >> shift_count);
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/* calc carry */
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msk_start = 32 - shift_count;
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msk = ((1 << shift_count) - 1) << msk_start;
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tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
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/* calc v/sv bits */
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tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max);
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tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min);
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tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
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tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
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/* calc sv */
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tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV);
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/* do shift */
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tcg_gen_shli_tl(ret, r1, shift_count);
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tcg_temp_free(t_max);
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tcg_temp_free(t_min);
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} else {
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/* clear PSW.V */
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tcg_gen_movi_tl(cpu_PSW_V, 0);
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/* calc carry */
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msk = (1 << -shift_count) - 1;
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tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
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/* do shift */
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tcg_gen_sari_tl(ret, r1, -shift_count);
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}
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/* calc av overflow bit */
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tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
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tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
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/* calc sav overflow bit */
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tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
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tcg_temp_free(temp);
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tcg_temp_free(temp2);
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tcg_temp_free(t_0);
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}
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/*
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* Functions for decoding instructions
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*/
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static void decode_src_opc(DisasContext *ctx, int op1)
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{
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int r1;
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int32_t const4;
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TCGv temp, temp2;
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r1 = MASK_OP_SRC_S1D(ctx->opcode);
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const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode);
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switch (op1) {
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case OPC1_16_SRC_ADD:
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gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
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break;
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case OPC1_16_SRC_ADD_A15:
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gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4);
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break;
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case OPC1_16_SRC_ADD_15A:
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gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4);
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break;
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case OPC1_16_SRC_ADD_A:
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tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4);
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break;
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case OPC1_16_SRC_CADD:
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gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
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cpu_gpr_d[15]);
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break;
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case OPC1_16_SRC_CADDN:
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gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
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cpu_gpr_d[15]);
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break;
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case OPC1_16_SRC_CMOV:
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temp = tcg_const_tl(0);
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temp2 = tcg_const_tl(const4);
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tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
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temp2, cpu_gpr_d[r1]);
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tcg_temp_free(temp);
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tcg_temp_free(temp2);
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break;
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case OPC1_16_SRC_CMOVN:
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temp = tcg_const_tl(0);
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temp2 = tcg_const_tl(const4);
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tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
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temp2, cpu_gpr_d[r1]);
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tcg_temp_free(temp);
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tcg_temp_free(temp2);
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break;
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case OPC1_16_SRC_EQ:
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tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
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const4);
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break;
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case OPC1_16_SRC_LT:
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tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
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const4);
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break;
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case OPC1_16_SRC_MOV:
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tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
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break;
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case OPC1_16_SRC_MOV_A:
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const4 = MASK_OP_SRC_CONST4(ctx->opcode);
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tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
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break;
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case OPC1_16_SRC_SH:
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gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
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break;
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case OPC1_16_SRC_SHA:
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gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
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break;
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}
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}
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static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
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{
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int op1;
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op1 = MASK_OP_MAJOR(ctx->opcode);
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switch (op1) {
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case OPC1_16_SRC_ADD:
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case OPC1_16_SRC_ADD_A15:
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case OPC1_16_SRC_ADD_15A:
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case OPC1_16_SRC_ADD_A:
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case OPC1_16_SRC_CADD:
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case OPC1_16_SRC_CADDN:
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case OPC1_16_SRC_CMOV:
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case OPC1_16_SRC_CMOVN:
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case OPC1_16_SRC_EQ:
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case OPC1_16_SRC_LT:
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case OPC1_16_SRC_MOV:
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case OPC1_16_SRC_MOV_A:
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case OPC1_16_SRC_SH:
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case OPC1_16_SRC_SHA:
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decode_src_opc(ctx, op1);
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break;
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}
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}
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static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
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