arm_gic: Rename GIC_X_TRIGGER to GIC_X_EDGE_TRIGGER
TRIGGER can really mean mean anything (e.g. was it triggered, is it level-triggered, is it edge-triggered, etc.). Rename to EDGE_TRIGGER to make the code comprehensible without looking up the data structure. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1387606179-22709-2-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -128,7 +128,7 @@ static void gic_set_irq(void *opaque, int irq, int level)
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if (level) {
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GIC_SET_LEVEL(irq, cm);
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if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) {
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if (GIC_TEST_EDGE_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) {
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DPRINTF("Set %d pending mask %x\n", irq, target);
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GIC_SET_PENDING(irq, target);
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}
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@ -188,7 +188,7 @@ void gic_complete_irq(GICState *s, int cpu, int irq)
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return; /* No active IRQ. */
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/* Mark level triggered interrupts as pending if they are still
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raised. */
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if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm)
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if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm)
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&& GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) {
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DPRINTF("Set %d pending mask %x\n", irq, cm);
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GIC_SET_PENDING(irq, cm);
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@ -311,7 +311,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset)
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for (i = 0; i < 4; i++) {
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if (GIC_TEST_MODEL(irq + i))
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res |= (1 << (i * 2));
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if (GIC_TEST_TRIGGER(irq + i))
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if (GIC_TEST_EDGE_TRIGGER(irq + i))
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res |= (2 << (i * 2));
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}
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} else if (offset < 0xfe0) {
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@ -386,7 +386,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
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/* If a raised level triggered IRQ enabled then mark
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is as pending. */
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if (GIC_TEST_LEVEL(irq + i, mask)
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&& !GIC_TEST_TRIGGER(irq + i)) {
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&& !GIC_TEST_EDGE_TRIGGER(irq + i)) {
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DPRINTF("Set %d pending mask %x\n", irq + i, mask);
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GIC_SET_PENDING(irq + i, mask);
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}
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@ -478,9 +478,9 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
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GIC_CLEAR_MODEL(irq + i);
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}
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if (value & (2 << (i * 2))) {
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GIC_SET_TRIGGER(irq + i);
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GIC_SET_EDGE_TRIGGER(irq + i);
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} else {
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GIC_CLEAR_TRIGGER(irq + i);
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GIC_CLEAR_EDGE_TRIGGER(irq + i);
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}
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}
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} else {
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@ -51,7 +51,7 @@ static const VMStateDescription vmstate_gic_irq_state = {
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VMSTATE_UINT8(active, gic_irq_state),
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VMSTATE_UINT8(level, gic_irq_state),
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VMSTATE_BOOL(model, gic_irq_state),
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VMSTATE_BOOL(trigger, gic_irq_state),
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VMSTATE_BOOL(edge_trigger, gic_irq_state),
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VMSTATE_END_OF_LIST()
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}
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};
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@ -126,7 +126,7 @@ static void arm_gic_common_reset(DeviceState *dev)
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}
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for (i = 0; i < 16; i++) {
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GIC_SET_ENABLED(i, ALL_CPU_MASK);
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GIC_SET_TRIGGER(i);
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GIC_SET_EDGE_TRIGGER(i);
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}
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if (s->num_cpu == 1) {
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/* For uniprocessor GICs all interrupts always target the sole CPU */
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@ -44,9 +44,9 @@
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#define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
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#define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
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#define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
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#define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = true
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#define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = false
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#define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
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#define GIC_SET_EDGE_TRIGGER(irq) s->irq_state[irq].edge_trigger = true
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#define GIC_CLEAR_EDGE_TRIGGER(irq) s->irq_state[irq].edge_trigger = false
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#define GIC_TEST_EDGE_TRIGGER(irq) (s->irq_state[irq].edge_trigger)
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#define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \
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s->priority1[irq][cpu] : \
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s->priority2[(irq) - GIC_INTERNAL])
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@ -37,7 +37,7 @@ typedef struct gic_irq_state {
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uint8_t active;
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uint8_t level;
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bool model; /* 0 = N:N, 1 = 1:N */
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bool trigger; /* nonzero = edge triggered. */
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bool edge_trigger; /* true: edge-triggered, false: level-triggered */
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} gic_irq_state;
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typedef struct GICState {
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