hw/arm/armsse: Add SSE-200 model
Add a model of the SSE-200, now we have put in all the code that lets us make it different from the IoTKit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-22-peter.maydell@linaro.org
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@ -50,6 +50,18 @@ static const ARMSSEInfo armsse_variants[] = {
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.has_cpusecctrl = false,
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.has_cpuid = false,
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},
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{
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.name = TYPE_SSE200,
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.sram_banks = 4,
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.num_cpus = 2,
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.sys_version = 0x22041743,
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.sys_config_format = SSE200Format,
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.has_mhus = true,
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.has_ppus = true,
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.has_cachectrl = true,
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.has_cpusecctrl = true,
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.has_cpuid = true,
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},
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};
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static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info)
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@ -1,5 +1,5 @@
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/*
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* ARM SSE (Subsystems for Embedded): IoTKit
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* ARM SSE (Subsystems for Embedded): IoTKit, SSE-200
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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@ -12,9 +12,13 @@
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/*
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* This is a model of the Arm "Subsystems for Embedded" family of
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* hardware, which include the IoT Kit and the SSE-050, SSE-100 and
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* SSE-200. Currently we model only the Arm IoT Kit which is documented in
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* SSE-200. Currently we model:
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* - the Arm IoT Kit which is documented in
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* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
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* It contains:
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* - the SSE-200 which is documented in
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* http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
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*
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* The IoTKit contains:
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* a Cortex-M33
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* the IDAU
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* some timers and watchdogs
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@ -23,6 +27,14 @@
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* a security controller
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* a bus fabric which arranges that some parts of the address
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* space are secure and non-secure aliases of each other
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* The SSE-200 additionally contains:
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* a second Cortex-M33
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* two Message Handling Units (MHUs)
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* an optional CryptoCell (which we do not model)
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* more SRAM banks with associated MPCs
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* multiple Power Policy Units (PPUs)
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* a control interface for an icache for each CPU
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* per-CPU identity and control register blocks
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*
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* QEMU interface:
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* + QOM property "memory" is a MemoryRegion containing the devices provided
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@ -93,6 +105,7 @@
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* them via the ARMSSE base class, so they have no IOTKIT() etc macros.
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*/
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#define TYPE_IOTKIT "iotkit"
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#define TYPE_SSE200 "sse-200"
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/* We have an IRQ splitter and an OR gate input for each external PPC
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* and the 2 internal PPCs
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