target-cris/translate.c: Remove t_gen_mov_TN_reg and t_gen_mov_reg_TN

Remove the t_gen_mov_TN_reg and t_gen_mov_reg_TN wrappers: the
latter is completely unused, and the former only used in a few
places (which are thus inconsistent with the rest of the decoder
which directly accesses cpu_R[]).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
This commit is contained in:
Peter Maydell 2014-06-07 18:03:01 +01:00 committed by Edgar E. Iglesias
parent a373cdb5ce
commit 08397c4b29
2 changed files with 4 additions and 19 deletions

View file

@ -164,21 +164,6 @@ static int preg_sizes[] = {
#define t_gen_mov_env_TN(member, tn) \
_t_gen_mov_env_TN(offsetof(CPUCRISState, member), (tn))
static inline void t_gen_mov_TN_reg(TCGv tn, int r)
{
if (r < 0 || r > 15) {
fprintf(stderr, "wrong register read $r%d\n", r);
}
tcg_gen_mov_tl(tn, cpu_R[r]);
}
static inline void t_gen_mov_reg_TN(int r, TCGv tn)
{
if (r < 0 || r > 15) {
fprintf(stderr, "wrong register write $r%d\n", r);
}
tcg_gen_mov_tl(cpu_R[r], tn);
}
static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
{
if (offset > sizeof(CPUCRISState)) {
@ -1812,7 +1797,7 @@ static int dec_swap_r(CPUCRISState *env, DisasContext *dc)
cris_cc_mask(dc, CC_MASK_NZ);
t0 = tcg_temp_new();
t_gen_mov_TN_reg(t0, dc->op1);
tcg_gen_mov_tl(t0, cpu_R[dc->op1]);
if (dc->op2 & 8) {
tcg_gen_not_tl(t0, t0);
}
@ -2120,7 +2105,7 @@ static int dec_move_rp(CPUCRISState *env, DisasContext *dc)
t[0] = tcg_temp_new();
if (dc->op2 == PR_CCS) {
cris_evaluate_flags(dc);
t_gen_mov_TN_reg(t[0], dc->op1);
tcg_gen_mov_tl(t[0], cpu_R[dc->op1]);
if (dc->tb_flags & U_FLAG) {
t[1] = tcg_temp_new();
/* User space is not allowed to touch all flags. */
@ -2130,7 +2115,7 @@ static int dec_move_rp(CPUCRISState *env, DisasContext *dc)
tcg_temp_free(t[1]);
}
} else {
t_gen_mov_TN_reg(t[0], dc->op1);
tcg_gen_mov_tl(t[0], cpu_R[dc->op1]);
}
t_gen_mov_preg_TN(dc, dc->op2, t[0]);

View file

@ -516,7 +516,7 @@ static void dec10_reg_swap(DisasContext *dc)
cris_cc_mask(dc, CC_MASK_NZVC);
t0 = tcg_temp_new();
t_gen_mov_TN_reg(t0, dc->src);
tcg_gen_mov_tl(t0, cpu_R[dc->src]);
if (dc->dst & 8)
tcg_gen_not_tl(t0, t0);
if (dc->dst & 4)