riscv: sifive_e: Manually define the machine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
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@ -79,7 +79,7 @@ static void riscv_sifive_e_init(MachineState *machine)
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{
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const struct MemmapEntry *memmap = sifive_e_memmap;
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SiFiveEState *s = g_new0(SiFiveEState, 1);
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SiFiveEState *s = RISCV_E_MACHINE(machine);
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MemoryRegion *sys_mem = get_system_memory();
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MemoryRegion *main_mem = g_new(MemoryRegion, 1);
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int i;
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@ -115,6 +115,35 @@ static void riscv_sifive_e_init(MachineState *machine)
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}
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}
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static void sifive_e_machine_instance_init(Object *obj)
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{
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}
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static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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mc->desc = "RISC-V Board compatible with SiFive E SDK";
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mc->init = riscv_sifive_e_init;
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mc->max_cpus = 1;
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mc->default_cpu_type = SIFIVE_E_CPU;
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}
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static const TypeInfo sifive_e_machine_typeinfo = {
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.name = MACHINE_TYPE_NAME("sifive_e"),
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.parent = TYPE_MACHINE,
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.class_init = sifive_e_machine_class_init,
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.instance_init = sifive_e_machine_instance_init,
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.instance_size = sizeof(SiFiveEState),
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};
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static void sifive_e_machine_init_register_types(void)
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{
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type_register_static(&sifive_e_machine_typeinfo);
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}
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type_init(sifive_e_machine_init_register_types)
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static void riscv_sifive_e_soc_init(Object *obj)
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{
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MachineState *ms = MACHINE(qdev_get_machine());
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@ -214,16 +243,6 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
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&s->xip_mem);
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}
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static void riscv_sifive_e_machine_init(MachineClass *mc)
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{
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mc->desc = "RISC-V Board compatible with SiFive E SDK";
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mc->init = riscv_sifive_e_init;
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mc->max_cpus = 1;
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mc->default_cpu_type = SIFIVE_E_CPU;
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}
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DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
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static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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@ -47,6 +47,10 @@ typedef struct SiFiveEState {
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SiFiveESoCState soc;
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} SiFiveEState;
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#define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
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#define RISCV_E_MACHINE(obj) \
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OBJECT_CHECK(SiFiveEState, (obj), TYPE_RISCV_E_MACHINE)
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enum {
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SIFIVE_E_DEBUG,
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SIFIVE_E_MROM,
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