partial big endian fixes - change VESA VBE ports for non i386 targets to avoid unaligned accesses
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@866 c046a42c-6fe2-441c-8c8c-71466251a162
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642012017c
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09a79b4974
78
hw/vga.c
78
hw/vga.c
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@ -489,15 +489,19 @@ static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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}
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#ifdef CONFIG_BOCHS_VBE
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static uint32_t vbe_ioport_read(void *opaque, uint32_t addr)
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static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
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{
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VGAState *s = opaque;
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uint32_t val;
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val = s->vbe_index;
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return val;
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}
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static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
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{
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VGAState *s = opaque;
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uint32_t val;
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addr &= 1;
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if (addr == 0) {
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val = s->vbe_index;
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} else {
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if (s->vbe_index <= VBE_DISPI_INDEX_NB)
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val = s->vbe_regs[s->vbe_index];
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else
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@ -505,18 +509,20 @@ static uint32_t vbe_ioport_read(void *opaque, uint32_t addr)
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#ifdef DEBUG_BOCHS_VBE
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printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
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#endif
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}
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return val;
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}
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static void vbe_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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static void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
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{
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VGAState *s = opaque;
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s->vbe_index = val;
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}
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static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
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{
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VGAState *s = opaque;
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addr &= 1;
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if (addr == 0) {
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s->vbe_index = val;
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} else if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
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if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
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#ifdef DEBUG_BOCHS_VBE
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printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
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#endif
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@ -709,18 +715,30 @@ static uint32_t vga_mem_readb(target_phys_addr_t addr)
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static uint32_t vga_mem_readw(target_phys_addr_t addr)
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{
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uint32_t v;
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#ifdef TARGET_WORDS_BIGENDIAN
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v = vga_mem_readb(addr) << 8;
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v |= vga_mem_readb(addr + 1);
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#else
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v = vga_mem_readb(addr);
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v |= vga_mem_readb(addr + 1) << 8;
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#endif
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return v;
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}
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static uint32_t vga_mem_readl(target_phys_addr_t addr)
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{
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uint32_t v;
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#ifdef TARGET_WORDS_BIGENDIAN
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v = vga_mem_readb(addr) << 24;
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v |= vga_mem_readb(addr + 1) << 16;
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v |= vga_mem_readb(addr + 2) << 8;
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v |= vga_mem_readb(addr + 3);
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#else
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v = vga_mem_readb(addr);
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v |= vga_mem_readb(addr + 1) << 8;
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v |= vga_mem_readb(addr + 2) << 16;
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v |= vga_mem_readb(addr + 3) << 24;
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#endif
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return v;
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}
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@ -855,16 +873,28 @@ static void vga_mem_writeb(target_phys_addr_t addr, uint32_t val)
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static void vga_mem_writew(target_phys_addr_t addr, uint32_t val)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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vga_mem_writeb(addr, (val >> 8) & 0xff);
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vga_mem_writeb(addr + 1, val & 0xff);
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#else
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vga_mem_writeb(addr, val & 0xff);
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vga_mem_writeb(addr + 1, (val >> 8) & 0xff);
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#endif
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}
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static void vga_mem_writel(target_phys_addr_t addr, uint32_t val)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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vga_mem_writeb(addr, (val >> 24) & 0xff);
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vga_mem_writeb(addr + 1, (val >> 16) & 0xff);
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vga_mem_writeb(addr + 2, (val >> 8) & 0xff);
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vga_mem_writeb(addr + 3, val & 0xff);
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#else
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vga_mem_writeb(addr, val & 0xff);
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vga_mem_writeb(addr + 1, (val >> 8) & 0xff);
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vga_mem_writeb(addr + 2, (val >> 16) & 0xff);
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vga_mem_writeb(addr + 3, (val >> 24) & 0xff);
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#endif
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}
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typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
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@ -1774,19 +1804,27 @@ int vga_initialize(DisplayState *ds, uint8_t *vga_ram_base,
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#ifdef CONFIG_BOCHS_VBE
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s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
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s->vbe_bank_mask = ((s->vram_size >> 16) - 1);
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register_ioport_read(0x1ce, 1, 2, vbe_ioport_read, s);
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register_ioport_read(0x1cf, 1, 2, vbe_ioport_read, s);
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#if defined (TARGET_I386)
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register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
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register_ioport_read(0x1cf, 1, 2, vbe_ioport_read_data, s);
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register_ioport_write(0x1ce, 1, 2, vbe_ioport_write, s);
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register_ioport_write(0x1cf, 1, 2, vbe_ioport_write, s);
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register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
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register_ioport_write(0x1cf, 1, 2, vbe_ioport_write_data, s);
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/* old Bochs IO ports */
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register_ioport_read(0xff80, 1, 2, vbe_ioport_read, s);
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register_ioport_read(0xff81, 1, 2, vbe_ioport_read, s);
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register_ioport_read(0xff80, 1, 2, vbe_ioport_read_index, s);
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register_ioport_read(0xff81, 1, 2, vbe_ioport_read_data, s);
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register_ioport_write(0xff80, 1, 2, vbe_ioport_write, s);
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register_ioport_write(0xff81, 1, 2, vbe_ioport_write, s);
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register_ioport_write(0xff80, 1, 2, vbe_ioport_write_index, s);
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register_ioport_write(0xff81, 1, 2, vbe_ioport_write_data, s);
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#else
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register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
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register_ioport_read(0x1d0, 1, 2, vbe_ioport_read_data, s);
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register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
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register_ioport_write(0x1d0, 1, 2, vbe_ioport_write_data, s);
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#endif
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#endif /* CONFIG_BOCHS_VBE */
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vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write);
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cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
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@ -1814,11 +1852,9 @@ int vga_initialize(DisplayState *ds, uint8_t *vga_ram_base,
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PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
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} else {
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#ifdef CONFIG_BOCHS_VBE
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#if defined (TARGET_I386)
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/* XXX: use optimized standard vga accesses */
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cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
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vga_ram_size, vga_ram_offset);
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#endif
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#endif
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}
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return 0;
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