target/riscv: Trigger interrupt on MIP update asynchronously
The requirement of holding the iothread_mutex is burdersome when swapping the background and foreground registers in the Hypervisor extension. To avoid the requrirement let's set the interrupt asynchronously. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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@ -82,10 +82,31 @@ int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
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}
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}
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/* iothread_mutex must be held */
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struct CpuAsyncInfo {
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uint32_t new_mip;
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};
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static void riscv_cpu_update_mip_irqs_async(CPUState *target_cpu_state,
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run_on_cpu_data data)
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{
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CPURISCVState *env = &RISCV_CPU(target_cpu_state)->env;
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RISCVCPU *cpu = riscv_env_get_cpu(env);
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struct CpuAsyncInfo *info = (struct CpuAsyncInfo *) data.host_ptr;
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if (info->new_mip) {
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cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
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} else {
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cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
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}
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g_free(info);
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}
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uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
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{
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CPURISCVState *env = &cpu->env;
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CPUState *cs = CPU(cpu);
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struct CpuAsyncInfo *info;
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uint32_t old, new, cmp = atomic_read(&env->mip);
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do {
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@ -94,11 +115,11 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
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cmp = atomic_cmpxchg(&env->mip, old, new);
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} while (old != cmp);
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if (new) {
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cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
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} else {
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cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
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}
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info = g_new(struct CpuAsyncInfo, 1);
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info->new_mip = new;
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async_run_on_cpu(cs, riscv_cpu_update_mip_irqs_async,
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RUN_ON_CPU_HOST_PTR(info));
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return old;
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}
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@ -555,9 +555,7 @@ static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
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uint32_t old_mip;
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if (mask) {
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qemu_mutex_lock_iothread();
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old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
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qemu_mutex_unlock_iothread();
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} else {
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old_mip = atomic_read(&env->mip);
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}
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