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target/mips: Implement MT ASE support for nanoMIPS

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Add emulation of MT ASE instructions for nanoMIPS.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
This commit is contained in:
Stefan Markovic 2018-08-02 16:16:24 +02:00 committed by Aleksandar Markovic
parent 9affc1c592
commit 0a1a6ed78a
1 changed files with 83 additions and 2 deletions
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85
target/mips/translate.c
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@ -16989,7 +16989,7 @@ static void gen_pool16c_nanomips_insn(DisasContext *ctx)
}
}
static void gen_pool32a0_nanomips_insn(DisasContext *ctx)
static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
{
int rt = extract32(ctx->opcode, 21, 5);
int rs = extract32(ctx->opcode, 16, 5);
@ -17157,6 +17157,87 @@ static void gen_pool32a0_nanomips_insn(DisasContext *ctx)
tcg_temp_free(t0);
}
break;
case NM_D_E_MT_VPE:
{
uint8_t sc = extract32(ctx->opcode, 10, 1);
TCGv t0 = tcg_temp_new();
switch (sc) {
case 0:
if (rs == 1) {
/* DMT */
check_cp0_mt(ctx);
gen_helper_dmt(t0);
gen_store_gpr(t0, rt);
} else if (rs == 0) {
/* DVPE */
check_cp0_mt(ctx);
gen_helper_dvpe(t0, cpu_env);
gen_store_gpr(t0, rt);
} else {
generate_exception_end(ctx, EXCP_RI);
}
break;
case 1:
if (rs == 1) {
/* EMT */
check_cp0_mt(ctx);
gen_helper_emt(t0);
gen_store_gpr(t0, rt);
} else if (rs == 0) {
/* EVPE */
check_cp0_mt(ctx);
gen_helper_evpe(t0, cpu_env);
gen_store_gpr(t0, rt);
} else {
generate_exception_end(ctx, EXCP_RI);
}
break;
}
tcg_temp_free(t0);
}
break;
case NM_FORK:
check_mt(ctx);
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
gen_load_gpr(t0, rt);
gen_load_gpr(t1, rs);
gen_helper_fork(t0, t1);
tcg_temp_free(t0);
tcg_temp_free(t1);
}
break;
case NM_MFTR:
case NM_MFHTR:
check_cp0_enabled(ctx);
if (rd == 0) {
/* Treat as NOP. */
return;
}
gen_mftr(env, ctx, rs, rt, extract32(ctx->opcode, 10, 1),
extract32(ctx->opcode, 11, 5), extract32(ctx->opcode, 3, 1));
break;
case NM_MTTR:
case NM_MTHTR:
check_cp0_enabled(ctx);
gen_mttr(env, ctx, rs, rt, extract32(ctx->opcode, 10, 1),
extract32(ctx->opcode, 11, 5), extract32(ctx->opcode, 3, 1));
break;
case NM_YIELD:
check_mt(ctx);
{
TCGv t0 = tcg_temp_new();
gen_load_gpr(t0, rs);
gen_helper_yield(t0, cpu_env, t0);
gen_store_gpr(t0, rt);
tcg_temp_free(t0);
}
break;
#endif
default:
generate_exception_end(ctx, EXCP_RI);
@ -18049,7 +18130,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
case NM_POOL32A:
switch (ctx->opcode & 0x07) {
case NM_POOL32A0:
gen_pool32a0_nanomips_insn(ctx);
gen_pool32a0_nanomips_insn(env, ctx);
break;
case NM_POOL32A7:
switch (extract32(ctx->opcode, 3, 3)) {