target/riscv: vector widening saturating scaled multiply-add
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-28-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -751,3 +751,25 @@ DEF_HELPER_6(vsmul_vx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsmul_vx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsmul_vx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsmul_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsmul_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsmul_vx_d, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsmul_vx_d, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwsmaccu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwsmaccu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwsmaccu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwsmacc_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwsmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwsmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwsmaccsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwsmaccsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwsmaccsu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwsmaccu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwsmaccu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwsmaccu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwsmacc_vx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwsmacc_vx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwsmacc_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwsmaccsu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwsmaccsu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwsmaccsu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwsmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwsmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwsmaccus_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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@ -426,6 +426,13 @@ vasub_vv 100110 . ..... ..... 000 ..... 1010111 @r_vm
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vasub_vx 100110 . ..... ..... 100 ..... 1010111 @r_vm
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vasub_vx 100110 . ..... ..... 100 ..... 1010111 @r_vm
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vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm
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vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm
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vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm
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vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm
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vwsmaccu_vv 111100 . ..... ..... 000 ..... 1010111 @r_vm
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vwsmaccu_vx 111100 . ..... ..... 100 ..... 1010111 @r_vm
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vwsmacc_vv 111101 . ..... ..... 000 ..... 1010111 @r_vm
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vwsmacc_vx 111101 . ..... ..... 100 ..... 1010111 @r_vm
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vwsmaccsu_vv 111110 . ..... ..... 000 ..... 1010111 @r_vm
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vwsmaccsu_vx 111110 . ..... ..... 100 ..... 1010111 @r_vm
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vwsmaccus_vx 111111 . ..... ..... 100 ..... 1010111 @r_vm
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vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
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vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
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vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
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vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
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@ -1758,3 +1758,12 @@ GEN_OPIVI_TRANS(vaadd_vi, 0, vaadd_vx, opivx_check)
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/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
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/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
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GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
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GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
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GEN_OPIVX_TRANS(vsmul_vx, opivx_check)
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GEN_OPIVX_TRANS(vsmul_vx, opivx_check)
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/* Vector Widening Saturating Scaled Multiply-Add */
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GEN_OPIVV_WIDEN_TRANS(vwsmaccu_vv, opivv_widen_check)
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GEN_OPIVV_WIDEN_TRANS(vwsmacc_vv, opivv_widen_check)
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GEN_OPIVV_WIDEN_TRANS(vwsmaccsu_vv, opivv_widen_check)
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GEN_OPIVX_WIDEN_TRANS(vwsmaccu_vx)
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GEN_OPIVX_WIDEN_TRANS(vwsmacc_vx)
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GEN_OPIVX_WIDEN_TRANS(vwsmaccsu_vx)
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GEN_OPIVX_WIDEN_TRANS(vwsmaccus_vx)
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@ -2704,3 +2704,208 @@ GEN_VEXT_VX_RM(vsmul_vx_b, 1, 1, clearb)
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GEN_VEXT_VX_RM(vsmul_vx_h, 2, 2, clearh)
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GEN_VEXT_VX_RM(vsmul_vx_h, 2, 2, clearh)
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GEN_VEXT_VX_RM(vsmul_vx_w, 4, 4, clearl)
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GEN_VEXT_VX_RM(vsmul_vx_w, 4, 4, clearl)
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GEN_VEXT_VX_RM(vsmul_vx_d, 8, 8, clearq)
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GEN_VEXT_VX_RM(vsmul_vx_d, 8, 8, clearq)
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/* Vector Widening Saturating Scaled Multiply-Add */
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static inline uint16_t
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vwsmaccu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b,
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uint16_t c)
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{
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uint8_t round;
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uint16_t res = (uint16_t)a * b;
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round = get_round(vxrm, res, 4);
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res = (res >> 4) + round;
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return saddu16(env, vxrm, c, res);
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}
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static inline uint32_t
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vwsmaccu16(CPURISCVState *env, int vxrm, uint16_t a, uint16_t b,
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uint32_t c)
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{
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uint8_t round;
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uint32_t res = (uint32_t)a * b;
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round = get_round(vxrm, res, 8);
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res = (res >> 8) + round;
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return saddu32(env, vxrm, c, res);
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}
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static inline uint64_t
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vwsmaccu32(CPURISCVState *env, int vxrm, uint32_t a, uint32_t b,
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uint64_t c)
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{
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uint8_t round;
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uint64_t res = (uint64_t)a * b;
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round = get_round(vxrm, res, 16);
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res = (res >> 16) + round;
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return saddu64(env, vxrm, c, res);
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}
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#define OPIVV3_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
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static inline void \
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do_##NAME(void *vd, void *vs1, void *vs2, int i, \
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CPURISCVState *env, int vxrm) \
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{ \
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TX1 s1 = *((T1 *)vs1 + HS1(i)); \
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TX2 s2 = *((T2 *)vs2 + HS2(i)); \
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TD d = *((TD *)vd + HD(i)); \
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*((TD *)vd + HD(i)) = OP(env, vxrm, s2, s1, d); \
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}
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RVVCALL(OPIVV3_RM, vwsmaccu_vv_b, WOP_UUU_B, H2, H1, H1, vwsmaccu8)
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RVVCALL(OPIVV3_RM, vwsmaccu_vv_h, WOP_UUU_H, H4, H2, H2, vwsmaccu16)
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RVVCALL(OPIVV3_RM, vwsmaccu_vv_w, WOP_UUU_W, H8, H4, H4, vwsmaccu32)
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GEN_VEXT_VV_RM(vwsmaccu_vv_b, 1, 2, clearh)
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GEN_VEXT_VV_RM(vwsmaccu_vv_h, 2, 4, clearl)
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GEN_VEXT_VV_RM(vwsmaccu_vv_w, 4, 8, clearq)
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#define OPIVX3_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
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static inline void \
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do_##NAME(void *vd, target_long s1, void *vs2, int i, \
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CPURISCVState *env, int vxrm) \
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{ \
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TX2 s2 = *((T2 *)vs2 + HS2(i)); \
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TD d = *((TD *)vd + HD(i)); \
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*((TD *)vd + HD(i)) = OP(env, vxrm, s2, (TX1)(T1)s1, d); \
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}
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RVVCALL(OPIVX3_RM, vwsmaccu_vx_b, WOP_UUU_B, H2, H1, vwsmaccu8)
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RVVCALL(OPIVX3_RM, vwsmaccu_vx_h, WOP_UUU_H, H4, H2, vwsmaccu16)
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RVVCALL(OPIVX3_RM, vwsmaccu_vx_w, WOP_UUU_W, H8, H4, vwsmaccu32)
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GEN_VEXT_VX_RM(vwsmaccu_vx_b, 1, 2, clearh)
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GEN_VEXT_VX_RM(vwsmaccu_vx_h, 2, 4, clearl)
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GEN_VEXT_VX_RM(vwsmaccu_vx_w, 4, 8, clearq)
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static inline int16_t
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vwsmacc8(CPURISCVState *env, int vxrm, int8_t a, int8_t b, int16_t c)
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{
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uint8_t round;
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int16_t res = (int16_t)a * b;
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round = get_round(vxrm, res, 4);
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res = (res >> 4) + round;
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return sadd16(env, vxrm, c, res);
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}
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static inline int32_t
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vwsmacc16(CPURISCVState *env, int vxrm, int16_t a, int16_t b, int32_t c)
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{
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uint8_t round;
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int32_t res = (int32_t)a * b;
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round = get_round(vxrm, res, 8);
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res = (res >> 8) + round;
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return sadd32(env, vxrm, c, res);
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}
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static inline int64_t
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vwsmacc32(CPURISCVState *env, int vxrm, int32_t a, int32_t b, int64_t c)
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{
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uint8_t round;
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int64_t res = (int64_t)a * b;
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round = get_round(vxrm, res, 16);
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res = (res >> 16) + round;
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return sadd64(env, vxrm, c, res);
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}
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RVVCALL(OPIVV3_RM, vwsmacc_vv_b, WOP_SSS_B, H2, H1, H1, vwsmacc8)
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RVVCALL(OPIVV3_RM, vwsmacc_vv_h, WOP_SSS_H, H4, H2, H2, vwsmacc16)
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RVVCALL(OPIVV3_RM, vwsmacc_vv_w, WOP_SSS_W, H8, H4, H4, vwsmacc32)
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GEN_VEXT_VV_RM(vwsmacc_vv_b, 1, 2, clearh)
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GEN_VEXT_VV_RM(vwsmacc_vv_h, 2, 4, clearl)
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GEN_VEXT_VV_RM(vwsmacc_vv_w, 4, 8, clearq)
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RVVCALL(OPIVX3_RM, vwsmacc_vx_b, WOP_SSS_B, H2, H1, vwsmacc8)
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RVVCALL(OPIVX3_RM, vwsmacc_vx_h, WOP_SSS_H, H4, H2, vwsmacc16)
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RVVCALL(OPIVX3_RM, vwsmacc_vx_w, WOP_SSS_W, H8, H4, vwsmacc32)
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GEN_VEXT_VX_RM(vwsmacc_vx_b, 1, 2, clearh)
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GEN_VEXT_VX_RM(vwsmacc_vx_h, 2, 4, clearl)
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GEN_VEXT_VX_RM(vwsmacc_vx_w, 4, 8, clearq)
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static inline int16_t
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vwsmaccsu8(CPURISCVState *env, int vxrm, uint8_t a, int8_t b, int16_t c)
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{
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uint8_t round;
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int16_t res = a * (int16_t)b;
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round = get_round(vxrm, res, 4);
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res = (res >> 4) + round;
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return ssub16(env, vxrm, c, res);
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}
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static inline int32_t
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vwsmaccsu16(CPURISCVState *env, int vxrm, uint16_t a, int16_t b, uint32_t c)
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{
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uint8_t round;
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int32_t res = a * (int32_t)b;
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round = get_round(vxrm, res, 8);
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res = (res >> 8) + round;
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return ssub32(env, vxrm, c, res);
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}
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static inline int64_t
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vwsmaccsu32(CPURISCVState *env, int vxrm, uint32_t a, int32_t b, int64_t c)
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{
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uint8_t round;
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int64_t res = a * (int64_t)b;
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round = get_round(vxrm, res, 16);
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res = (res >> 16) + round;
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return ssub64(env, vxrm, c, res);
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}
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RVVCALL(OPIVV3_RM, vwsmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, vwsmaccsu8)
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RVVCALL(OPIVV3_RM, vwsmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, vwsmaccsu16)
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RVVCALL(OPIVV3_RM, vwsmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, vwsmaccsu32)
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GEN_VEXT_VV_RM(vwsmaccsu_vv_b, 1, 2, clearh)
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GEN_VEXT_VV_RM(vwsmaccsu_vv_h, 2, 4, clearl)
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GEN_VEXT_VV_RM(vwsmaccsu_vv_w, 4, 8, clearq)
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RVVCALL(OPIVX3_RM, vwsmaccsu_vx_b, WOP_SSU_B, H2, H1, vwsmaccsu8)
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RVVCALL(OPIVX3_RM, vwsmaccsu_vx_h, WOP_SSU_H, H4, H2, vwsmaccsu16)
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RVVCALL(OPIVX3_RM, vwsmaccsu_vx_w, WOP_SSU_W, H8, H4, vwsmaccsu32)
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GEN_VEXT_VX_RM(vwsmaccsu_vx_b, 1, 2, clearh)
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GEN_VEXT_VX_RM(vwsmaccsu_vx_h, 2, 4, clearl)
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GEN_VEXT_VX_RM(vwsmaccsu_vx_w, 4, 8, clearq)
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static inline int16_t
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vwsmaccus8(CPURISCVState *env, int vxrm, int8_t a, uint8_t b, int16_t c)
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{
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uint8_t round;
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int16_t res = (int16_t)a * b;
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round = get_round(vxrm, res, 4);
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res = (res >> 4) + round;
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return ssub16(env, vxrm, c, res);
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}
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static inline int32_t
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vwsmaccus16(CPURISCVState *env, int vxrm, int16_t a, uint16_t b, int32_t c)
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{
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uint8_t round;
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int32_t res = (int32_t)a * b;
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round = get_round(vxrm, res, 8);
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res = (res >> 8) + round;
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return ssub32(env, vxrm, c, res);
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}
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static inline int64_t
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vwsmaccus32(CPURISCVState *env, int vxrm, int32_t a, uint32_t b, int64_t c)
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{
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uint8_t round;
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int64_t res = (int64_t)a * b;
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round = get_round(vxrm, res, 16);
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res = (res >> 16) + round;
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return ssub64(env, vxrm, c, res);
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}
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RVVCALL(OPIVX3_RM, vwsmaccus_vx_b, WOP_SUS_B, H2, H1, vwsmaccus8)
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RVVCALL(OPIVX3_RM, vwsmaccus_vx_h, WOP_SUS_H, H4, H2, vwsmaccus16)
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RVVCALL(OPIVX3_RM, vwsmaccus_vx_w, WOP_SUS_W, H8, H4, vwsmaccus32)
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GEN_VEXT_VX_RM(vwsmaccus_vx_b, 1, 2, clearh)
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GEN_VEXT_VX_RM(vwsmaccus_vx_h, 2, 4, clearl)
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GEN_VEXT_VX_RM(vwsmaccus_vx_w, 4, 8, clearq)
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|
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Loading…
Reference in a new issue