target/mips: fetch code with translator_ld
Similarly to commits ae82adc8e29..7f93879e444, use the
translator_ld*() API introduced in commit 409c1a0bf0
to fetch the code on the MIPS target.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210125105818.2707067-1-f4bug@amsat.org>
This commit is contained in:
parent
c0928e6ddc
commit
0ab8e33a48
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@ -26,7 +26,7 @@
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#include "cpu.h"
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#include "internal.h"
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#include "tcg/tcg-op.h"
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#include "exec/cpu_ldst.h"
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#include "exec/translator.h"
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#include "exec/helper-proto.h"
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#include "exec/helper-gen.h"
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#include "hw/semihosting/semihost.h"
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@ -13911,7 +13911,7 @@ static void decode_i64_mips16(DisasContext *ctx,
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static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
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{
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int extend = cpu_lduw_code(env, ctx->base.pc_next + 2);
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int extend = translator_lduw(env, ctx->base.pc_next + 2);
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int op, rx, ry, funct, sa;
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int16_t imm, offset;
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@ -14161,7 +14161,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
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/* No delay slot, so just process as a normal instruction */
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break;
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case M16_OPC_JAL:
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offset = cpu_lduw_code(env, ctx->base.pc_next + 2);
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offset = translator_lduw(env, ctx->base.pc_next + 2);
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offset = (((ctx->opcode & 0x1f) << 21)
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| ((ctx->opcode >> 5) & 0x1f) << 16
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| offset) << 2;
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@ -16295,7 +16295,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
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uint32_t op, minor, minor2, mips32_op;
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uint32_t cond, fmt, cc;
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insn = cpu_lduw_code(env, ctx->base.pc_next + 2);
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insn = translator_lduw(env, ctx->base.pc_next + 2);
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ctx->opcode = (ctx->opcode << 16) | insn;
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rt = (ctx->opcode >> 21) & 0x1f;
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@ -21350,7 +21350,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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int offset;
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int imm;
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insn = cpu_lduw_code(env, ctx->base.pc_next + 2);
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insn = translator_lduw(env, ctx->base.pc_next + 2);
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ctx->opcode = (ctx->opcode << 16) | insn;
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rt = extract32(ctx->opcode, 21, 5);
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@ -21469,7 +21469,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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break;
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case NM_P48I:
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{
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insn = cpu_lduw_code(env, ctx->base.pc_next + 4);
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insn = translator_lduw(env, ctx->base.pc_next + 4);
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target_long addr_off = extract32(ctx->opcode, 0, 16) | insn << 16;
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switch (extract32(ctx->opcode, 16, 5)) {
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case NM_LI48:
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@ -29087,17 +29087,17 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
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is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
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if (ctx->insn_flags & ISA_NANOMIPS32) {
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ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
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ctx->opcode = translator_lduw(env, ctx->base.pc_next);
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insn_bytes = decode_nanomips_opc(env, ctx);
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} else if (!(ctx->hflags & MIPS_HFLAG_M16)) {
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ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
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ctx->opcode = translator_ldl(env, ctx->base.pc_next);
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insn_bytes = 4;
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decode_opc(env, ctx);
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} else if (ctx->insn_flags & ASE_MICROMIPS) {
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ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
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ctx->opcode = translator_lduw(env, ctx->base.pc_next);
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insn_bytes = decode_micromips_opc(env, ctx);
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} else if (ctx->insn_flags & ASE_MIPS16) {
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ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
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ctx->opcode = translator_lduw(env, ctx->base.pc_next);
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insn_bytes = decode_mips16_opc(env, ctx);
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} else {
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gen_reserved_instruction(ctx);
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