target-i386: Fix lcall/ljmp to call gate in IA-32e mode
Currently call gates are always treated as 32-bit gates. In IA-32e mode (either compatibility or 64-bit submode), system segment descriptors are always 64-bit. Treating them as 32-bit has the expected unfortunate effect: only the lower 32 bits of the offset are loaded, the stack pointer is truncated, a bad new stack pointer is loaded from the TSS (if switching privilege levels), etc. This change adds support for 64-bit call gate to the lcall and ljmp instructions. Additionally, there should be a check for non-canonical stack pointers, but I've omitted that since there doesn't seem to be checks for non-canonical addresses in this code elsewhere. I've left the raise_exception_err_ra lines unwapped at 80 columns to match the style in the rest of the file. Signed-off-by: Andrew Oates <aoates@google.com> Message-Id: <20180819181725.34098-1-andrew@andrewoates.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -518,6 +518,11 @@ static void switch_tss(CPUX86State *env, int tss_selector,
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static inline unsigned int get_sp_mask(unsigned int e2)
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{
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#ifdef TARGET_X86_64
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if (e2 & DESC_L_MASK) {
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return 0;
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} else
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#endif
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if (e2 & DESC_B_MASK) {
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return 0xffffffff;
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} else {
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@ -1640,6 +1645,14 @@ void helper_ljmp_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
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rpl = new_cs & 3;
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cpl = env->hflags & HF_CPL_MASK;
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type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
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#ifdef TARGET_X86_64
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if (env->efer & MSR_EFER_LMA) {
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if (type != 12) {
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raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
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}
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}
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#endif
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switch (type) {
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case 1: /* 286 TSS */
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case 9: /* 386 TSS */
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@ -1662,6 +1675,23 @@ void helper_ljmp_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
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if (type == 12) {
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new_eip |= (e2 & 0xffff0000);
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}
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#ifdef TARGET_X86_64
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if (env->efer & MSR_EFER_LMA) {
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/* load the upper 8 bytes of the 64-bit call gate */
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if (load_segment_ra(env, &e1, &e2, new_cs + 8, GETPC())) {
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raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc,
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GETPC());
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}
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type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
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if (type != 0) {
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raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc,
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GETPC());
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}
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new_eip |= ((target_ulong)e1) << 32;
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}
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#endif
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if (load_segment_ra(env, &e1, &e2, gate_cs, GETPC()) != 0) {
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raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, GETPC());
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}
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@ -1675,11 +1705,22 @@ void helper_ljmp_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
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(!(e2 & DESC_C_MASK) && (dpl != cpl))) {
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raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, GETPC());
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}
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#ifdef TARGET_X86_64
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if (env->efer & MSR_EFER_LMA) {
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if (!(e2 & DESC_L_MASK)) {
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raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, GETPC());
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}
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if (e2 & DESC_B_MASK) {
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raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, GETPC());
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}
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}
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#endif
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if (!(e2 & DESC_P_MASK)) {
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raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, GETPC());
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}
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limit = get_seg_limit(e1, e2);
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if (new_eip > limit) {
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if (new_eip > limit &&
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(!(env->hflags & HF_LMA_MASK) || !(e2 & DESC_L_MASK))) {
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raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
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}
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cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) | cpl,
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@ -1724,12 +1765,12 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
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int shift, target_ulong next_eip)
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{
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int new_stack, i;
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uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count;
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uint32_t ss = 0, ss_e1 = 0, ss_e2 = 0, sp, type, ss_dpl, sp_mask;
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uint32_t e1, e2, cpl, dpl, rpl, selector, param_count;
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uint32_t ss = 0, ss_e1 = 0, ss_e2 = 0, type, ss_dpl, sp_mask;
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uint32_t val, limit, old_sp_mask;
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target_ulong ssp, old_ssp;
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target_ulong ssp, old_ssp, offset, sp;
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LOG_PCALL("lcall %04x:%08x s=%d\n", new_cs, (uint32_t)new_eip, shift);
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LOG_PCALL("lcall %04x:" TARGET_FMT_lx " s=%d\n", new_cs, new_eip, shift);
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LOG_PCALL_STATE(CPU(x86_env_get_cpu(env)));
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if ((new_cs & 0xfffc) == 0) {
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raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
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@ -1807,6 +1848,15 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
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type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
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dpl = (e2 >> DESC_DPL_SHIFT) & 3;
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rpl = new_cs & 3;
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#ifdef TARGET_X86_64
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if (env->efer & MSR_EFER_LMA) {
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if (type != 12) {
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raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
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}
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}
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#endif
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switch (type) {
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case 1: /* available 286 TSS */
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case 9: /* available 386 TSS */
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@ -1833,8 +1883,23 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
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raise_exception_err_ra(env, EXCP0B_NOSEG, new_cs & 0xfffc, GETPC());
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}
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selector = e1 >> 16;
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offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
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param_count = e2 & 0x1f;
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offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
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#ifdef TARGET_X86_64
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if (env->efer & MSR_EFER_LMA) {
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/* load the upper 8 bytes of the 64-bit call gate */
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if (load_segment_ra(env, &e1, &e2, new_cs + 8, GETPC())) {
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raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc,
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GETPC());
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}
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type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
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if (type != 0) {
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raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc,
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GETPC());
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}
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offset |= ((target_ulong)e1) << 32;
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}
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#endif
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if ((selector & 0xfffc) == 0) {
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raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
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}
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@ -1849,16 +1914,41 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
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if (dpl > cpl) {
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raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
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}
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#ifdef TARGET_X86_64
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if (env->efer & MSR_EFER_LMA) {
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if (!(e2 & DESC_L_MASK)) {
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raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
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}
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if (e2 & DESC_B_MASK) {
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raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
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}
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shift++;
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}
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#endif
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if (!(e2 & DESC_P_MASK)) {
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raise_exception_err_ra(env, EXCP0B_NOSEG, selector & 0xfffc, GETPC());
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}
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if (!(e2 & DESC_C_MASK) && dpl < cpl) {
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/* to inner privilege */
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get_ss_esp_from_tss(env, &ss, &sp, dpl, GETPC());
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#ifdef TARGET_X86_64
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if (shift == 2) {
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sp = get_rsp_from_tss(env, dpl);
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ss = dpl; /* SS = NULL selector with RPL = new CPL */
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new_stack = 1;
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sp_mask = 0;
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ssp = 0; /* SS base is always zero in IA-32e mode */
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LOG_PCALL("new ss:rsp=%04x:%016llx env->regs[R_ESP]="
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TARGET_FMT_lx "\n", ss, sp, env->regs[R_ESP]);
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} else
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#endif
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{
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uint32_t sp32;
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get_ss_esp_from_tss(env, &ss, &sp32, dpl, GETPC());
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LOG_PCALL("new ss:esp=%04x:%08x param_count=%d env->regs[R_ESP]="
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TARGET_FMT_lx "\n", ss, sp, param_count,
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TARGET_FMT_lx "\n", ss, sp32, param_count,
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env->regs[R_ESP]);
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sp = sp32;
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if ((ss & 0xfffc) == 0) {
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raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC());
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}
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@ -1881,14 +1971,23 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
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raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC());
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}
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sp_mask = get_sp_mask(ss_e2);
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ssp = get_seg_base(ss_e1, ss_e2);
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}
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/* push_size = ((param_count * 2) + 8) << shift; */
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old_sp_mask = get_sp_mask(env->segs[R_SS].flags);
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old_ssp = env->segs[R_SS].base;
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sp_mask = get_sp_mask(ss_e2);
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ssp = get_seg_base(ss_e1, ss_e2);
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if (shift) {
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#ifdef TARGET_X86_64
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if (shift == 2) {
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/* XXX: verify if new stack address is canonical */
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PUSHQ_RA(sp, env->segs[R_SS].selector, GETPC());
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PUSHQ_RA(sp, env->regs[R_ESP], GETPC());
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/* parameters aren't supported for 64-bit call gates */
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} else
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#endif
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if (shift == 1) {
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PUSHL_RA(ssp, sp, sp_mask, env->segs[R_SS].selector, GETPC());
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PUSHL_RA(ssp, sp, sp_mask, env->regs[R_ESP], GETPC());
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for (i = param_count - 1; i >= 0; i--) {
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@ -1917,7 +2016,13 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
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new_stack = 0;
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}
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if (shift) {
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#ifdef TARGET_X86_64
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if (shift == 2) {
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PUSHQ_RA(sp, env->segs[R_CS].selector, GETPC());
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PUSHQ_RA(sp, next_eip, GETPC());
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} else
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#endif
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if (shift == 1) {
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PUSHL_RA(ssp, sp, sp_mask, env->segs[R_CS].selector, GETPC());
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PUSHL_RA(ssp, sp, sp_mask, next_eip, GETPC());
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} else {
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@ -1928,12 +2033,19 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
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/* from this point, not restartable */
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if (new_stack) {
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#ifdef TARGET_X86_64
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if (shift == 2) {
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cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0);
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} else
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#endif
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{
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ss = (ss & ~3) | dpl;
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cpu_x86_load_seg_cache(env, R_SS, ss,
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ssp,
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get_seg_limit(ss_e1, ss_e2),
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ss_e2);
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}
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}
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selector = (selector & ~3) | dpl;
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cpu_x86_load_seg_cache(env, R_CS, selector,
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