G364 video adapter enhancement
This patch improves G364 video card emulation (used in MIPS Magnum machine): - Use memory dirty tracking to not refresh whole screen each time - Use macros for debugging messages - Add support for hardware cursor - Handle Y-panning - Raise irq at each screen redraw - Support retrieving of some registers - Add load/save support The emulation has been tested in Linux 2.1 and Windows NT 3.5, in 640x480, 800x600, 1024x768 and 1280x1024 resolutions. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6356 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32
parent
f0f2f976cf
commit
0add30cff4
661
hw/g364fb.c
661
hw/g364fb.c
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@ -1,7 +1,7 @@
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/*
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* QEMU G364 framebuffer Emulator.
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*
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* Copyright (c) 2007-2008 Hervé Poussineau
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* Copyright (c) 2007-2009 Herve Poussineau
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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@ -25,140 +25,275 @@
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//#define DEBUG_G364
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#ifdef DEBUG_G364
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#define DPRINTF(fmt, args...) \
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do { printf("g364: " fmt , ##args); } while (0)
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#else
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#define DPRINTF(fmt, args...) do {} while (0)
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#endif
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#define BADF(fmt, args...) \
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do { fprintf(stderr, "g364 ERROR: " fmt , ##args);} while (0)
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typedef struct G364State {
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unsigned int vram_size;
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uint8_t *vram_buffer;
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/* hardware */
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uint8_t *vram;
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ram_addr_t vram_offset;
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int vram_size;
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qemu_irq irq;
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/* registers */
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uint8_t color_palette[256][3];
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uint8_t cursor_palette[3][3];
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uint16_t cursor[512];
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uint32_t cursor_position;
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uint32_t ctla;
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uint8_t palette[256][3];
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uint32_t top_of_screen;
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uint32_t width, height; /* in pixels */
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/* display refresh support */
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DisplayState *ds;
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int graphic_mode;
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uint32_t scr_width, scr_height; /* in pixels */
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int depth;
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int blanked;
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} G364State;
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/*
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* graphic modes
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*/
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#define BPP 8
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#define PIXEL_WIDTH 8
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#include "g364fb_template.h"
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#undef BPP
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#undef PIXEL_WIDTH
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#define REG_ID 0x000000
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#define REG_BOOT 0x080000
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#define REG_DISPLAY 0x080118
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#define REG_VDISPLAY 0x080150
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#define REG_CTLA 0x080300
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#define REG_TOP 0x080400
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#define REG_CURS_PAL 0x080508
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#define REG_CURS_POS 0x080638
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#define REG_CLR_PAL 0x080800
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#define REG_CURS_PAT 0x081000
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#define REG_RESET 0x180000
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#define BPP 15
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#define PIXEL_WIDTH 16
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#include "g364fb_template.h"
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#undef BPP
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#undef PIXEL_WIDTH
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#define CTLA_FORCE_BLANK 0x00000400
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#define CTLA_NO_CURSOR 0x00800000
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#define BPP 16
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#define PIXEL_WIDTH 16
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#include "g364fb_template.h"
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#undef BPP
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#undef PIXEL_WIDTH
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#define BPP 32
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#define PIXEL_WIDTH 32
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#include "g364fb_template.h"
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#undef BPP
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#undef PIXEL_WIDTH
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#define REG_DISPLAYX 0x0918
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#define REG_DISPLAYY 0x0940
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#define CTLA_FORCE_BLANK 0x400
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static void g364fb_draw_graphic(G364State *s, int full_update)
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static inline int check_dirty(ram_addr_t page)
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{
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return cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG);
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}
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static inline void reset_dirty(G364State *s,
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ram_addr_t page_min, ram_addr_t page_max)
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{
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cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE - 1,
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VGA_DIRTY_FLAG);
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}
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static void g364fb_draw_graphic8(G364State *s)
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{
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int i, w;
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uint8_t *vram;
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uint8_t *data_display, *dd;
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ram_addr_t page, page_min, page_max;
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int x, y;
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int xmin, xmax;
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int ymin, ymax;
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int xcursor, ycursor;
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unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned int b);
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switch (ds_get_bits_per_pixel(s->ds)) {
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case 8:
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g364fb_draw_graphic8(s, full_update);
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rgb_to_pixel = rgb_to_pixel8;
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w = 1;
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break;
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case 15:
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g364fb_draw_graphic15(s, full_update);
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rgb_to_pixel = rgb_to_pixel15;
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w = 2;
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break;
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case 16:
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g364fb_draw_graphic16(s, full_update);
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rgb_to_pixel = rgb_to_pixel16;
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w = 2;
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break;
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case 32:
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g364fb_draw_graphic32(s, full_update);
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rgb_to_pixel = rgb_to_pixel32;
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w = 4;
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break;
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default:
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printf("g364fb: unknown depth %d\n", ds_get_bits_per_pixel(s->ds));
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BADF("unknown host depth %d\n", ds_get_bits_per_pixel(s->ds));
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return;
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}
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dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height);
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page = s->vram_offset;
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page_min = (ram_addr_t)-1;
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page_max = 0;
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x = y = 0;
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xmin = s->width;
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xmax = 0;
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ymin = s->height;
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ymax = 0;
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if (!(s->ctla & CTLA_NO_CURSOR)) {
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xcursor = s->cursor_position >> 12;
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ycursor = s->cursor_position & 0xfff;
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} else {
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xcursor = ycursor = -65;
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}
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vram = s->vram + s->top_of_screen;
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/* XXX: out of range in vram? */
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data_display = dd = ds_get_data(s->ds);
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while (y < s->height) {
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if (check_dirty(page)) {
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if (y < ymin)
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ymin = ymax = y;
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if (page_min == (ram_addr_t)-1)
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page_min = page;
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page_max = page;
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if (x < xmin)
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xmin = x;
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for (i = 0; i < TARGET_PAGE_SIZE; i++) {
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uint8_t index;
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unsigned int color;
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if (unlikely((y >= ycursor && y < ycursor + 64) &&
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(x >= xcursor && x < xcursor + 64))) {
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/* pointer area */
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int xdiff = x - xcursor;
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uint16_t curs = s->cursor[(y - ycursor) * 8 + xdiff / 8];
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int op = (curs >> ((xdiff & 7) * 2)) & 3;
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if (likely(op == 0)) {
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/* transparent */
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index = *vram;
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color = (*rgb_to_pixel)(
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s->color_palette[index][0],
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s->color_palette[index][1],
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s->color_palette[index][2]);
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} else {
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/* get cursor color */
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index = op - 1;
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color = (*rgb_to_pixel)(
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s->cursor_palette[index][0],
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s->cursor_palette[index][1],
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s->cursor_palette[index][2]);
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}
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} else {
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/* normal area */
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index = *vram;
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color = (*rgb_to_pixel)(
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s->color_palette[index][0],
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s->color_palette[index][1],
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s->color_palette[index][2]);
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}
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memcpy(dd, &color, w);
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dd += w;
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x++;
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vram++;
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if (x == s->width) {
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xmax = s->width - 1;
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y++;
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if (y == s->height) {
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ymax = s->height - 1;
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goto done;
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}
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data_display = dd = data_display + ds_get_linesize(s->ds);
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xmin = 0;
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x = 0;
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}
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}
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if (x > xmax)
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xmax = x;
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if (y > ymax)
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ymax = y;
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} else {
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int dy;
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if (page_min != (ram_addr_t)-1) {
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reset_dirty(s, page_min, page_max);
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page_min = (ram_addr_t)-1;
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page_max = 0;
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dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
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xmin = s->width;
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xmax = 0;
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ymin = s->height;
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ymax = 0;
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}
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x += TARGET_PAGE_SIZE;
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dy = x / s->width;
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x = x % s->width;
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y += dy;
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vram += TARGET_PAGE_SIZE;
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data_display += dy * ds_get_linesize(s->ds);
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dd = data_display + x * w;
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}
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page += TARGET_PAGE_SIZE;
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}
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done:
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if (page_min != (ram_addr_t)-1) {
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dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
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reset_dirty(s, page_min, page_max);
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}
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}
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static void g364fb_draw_blank(G364State *s, int full_update)
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static void g364fb_draw_blank(G364State *s)
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{
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int i, w;
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uint8_t *d;
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if (!full_update)
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if (s->blanked) {
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/* Screen is already blank. No need to redraw it */
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return;
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}
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w = s->scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
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w = s->width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
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d = ds_get_data(s->ds);
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for(i = 0; i < s->scr_height; i++) {
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for (i = 0; i < s->height; i++) {
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memset(d, 0, w);
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d += ds_get_linesize(s->ds);
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}
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dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height);
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dpy_update(s->ds, 0, 0, s->width, s->height);
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s->blanked = 1;
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}
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#define GMODE_GRAPH 0
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#define GMODE_BLANK 1
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static void g364fb_update_display(void *opaque)
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{
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G364State *s = opaque;
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int full_update, graphic_mode;
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if (s->scr_width == 0 || s->scr_height == 0)
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if (s->width == 0 || s->height == 0)
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return;
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if (s->ctla & CTLA_FORCE_BLANK)
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graphic_mode = GMODE_BLANK;
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else
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graphic_mode = GMODE_GRAPH;
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full_update = 0;
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if (graphic_mode != s->graphic_mode) {
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s->graphic_mode = graphic_mode;
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full_update = 1;
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if (s->width != ds_get_width(s->ds) || s->height != ds_get_height(s->ds)) {
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qemu_console_resize(s->ds, s->width, s->height);
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}
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if (s->scr_width != ds_get_width(s->ds) || s->scr_height != ds_get_height(s->ds)) {
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qemu_console_resize(s->ds, s->scr_width, s->scr_height);
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full_update = 1;
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}
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switch(graphic_mode) {
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case GMODE_GRAPH:
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g364fb_draw_graphic(s, full_update);
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break;
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case GMODE_BLANK:
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default:
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g364fb_draw_blank(s, full_update);
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break;
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if (s->ctla & CTLA_FORCE_BLANK) {
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g364fb_draw_blank(s);
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} else if (s->depth == 8) {
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g364fb_draw_graphic8(s);
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} else {
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BADF("unknown guest depth %d\n", s->depth);
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}
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qemu_irq_raise(s->irq);
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}
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/* force a full display refresh */
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static void g364fb_invalidate_display(void *opaque)
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static void inline g364fb_invalidate_display(void *opaque)
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{
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G364State *s = opaque;
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s->graphic_mode = -1; /* force full update */
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int i;
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s->blanked = 0;
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for (i = 0; i < s->vram_size; i += TARGET_PAGE_SIZE) {
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cpu_physical_memory_set_dirty(s->vram_offset + i);
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}
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}
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static void g364fb_reset(void *opaque)
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{
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G364State *s = opaque;
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qemu_irq_lower(s->irq);
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memset(s->palette, 0, sizeof(s->palette));
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s->scr_width = s->scr_height = 0;
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memset(s->vram_buffer, 0, s->vram_size);
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s->graphic_mode = -1; /* force full update */
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memset(s->color_palette, 0, sizeof(s->color_palette));
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memset(s->cursor_palette, 0, sizeof(s->cursor_palette));
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memset(s->cursor, 0, sizeof(s->cursor));
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s->cursor_position = 0;
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s->ctla = 0;
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s->top_of_screen = 0;
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s->width = s->height = 0;
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memset(s->vram, 0, s->vram_size);
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g364fb_invalidate_display(opaque);
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}
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static void g364fb_screen_dump(void *opaque, const char *filename)
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@ -169,117 +304,223 @@ static void g364fb_screen_dump(void *opaque, const char *filename)
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uint8_t *data_buffer;
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FILE *f;
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if (s->depth != 8) {
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BADF("unknown guest depth %d\n", s->depth);
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return;
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}
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f = fopen(filename, "wb");
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if (!f)
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return;
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data_buffer = s->vram_buffer;
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fprintf(f, "P6\n%d %d\n%d\n",
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s->scr_width, s->scr_height, 255);
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for(y = 0; y < s->scr_height; y++)
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for(x = 0; x < s->scr_width; x++, data_buffer++) {
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index = *data_buffer;
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fputc(s->palette[index][0], f);
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fputc(s->palette[index][1], f);
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fputc(s->palette[index][2], f);
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if (s->ctla & CTLA_FORCE_BLANK) {
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/* blank screen */
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fprintf(f, "P4\n%d %d\n",
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s->width, s->height);
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for (y = 0; y < s->height; y++)
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for (x = 0; x < s->width; x++)
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fputc(0, f);
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} else {
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data_buffer = s->vram + s->top_of_screen;
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fprintf(f, "P6\n%d %d\n%d\n",
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s->width, s->height, 255);
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for (y = 0; y < s->height; y++)
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for (x = 0; x < s->width; x++, data_buffer++) {
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index = *data_buffer;
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fputc(s->color_palette[index][0], f);
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fputc(s->color_palette[index][1], f);
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fputc(s->color_palette[index][2], f);
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}
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}
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fclose(f);
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}
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/* called for accesses to io ports */
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static uint32_t g364fb_ctrl_readb(void *opaque, target_phys_addr_t addr)
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static uint32_t g364fb_ctrl_readl(void *opaque, target_phys_addr_t addr)
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{
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//G364State *s = opaque;
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G364State *s = opaque;
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uint32_t val;
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addr &= 0xffff;
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switch (addr) {
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default:
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#ifdef DEBUG_G364
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printf("g364fb/ctrl: invalid read at [" TARGET_FMT_lx "]\n", addr);
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#endif
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val = 0;
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break;
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if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) {
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/* cursor pattern */
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int idx = (addr - REG_CURS_PAT) >> 3;
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val = s->cursor[idx];
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} else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) {
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/* cursor palette */
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int idx = (addr - REG_CURS_PAL) >> 3;
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val = ((uint32_t)s->cursor_palette[idx][0] << 16);
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val |= ((uint32_t)s->cursor_palette[idx][1] << 8);
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val |= ((uint32_t)s->cursor_palette[idx][2] << 0);
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} else {
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switch (addr) {
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case REG_ID:
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val = 0x10; /* Mips G364 */
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break;
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case REG_DISPLAY:
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val = s->width / 4;
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break;
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case REG_VDISPLAY:
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val = s->height * 2;
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break;
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case REG_CTLA:
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val = s->ctla;
|
||||
break;
|
||||
default:
|
||||
{
|
||||
BADF("invalid read at [" TARGET_FMT_plx "]\n", addr);
|
||||
val = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef DEBUG_G364
|
||||
printf("g364fb/ctrl: read 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
|
||||
#endif
|
||||
DPRINTF("read 0x%08x at [" TARGET_FMT_plx "]\n", val, addr);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static uint32_t g364fb_ctrl_readw(void *opaque, target_phys_addr_t addr)
|
||||
{
|
||||
uint32_t v;
|
||||
v = g364fb_ctrl_readb(opaque, addr);
|
||||
v |= g364fb_ctrl_readb(opaque, addr + 1) << 8;
|
||||
return v;
|
||||
uint32_t v = g364fb_ctrl_readl(opaque, addr & ~0x3);
|
||||
if (addr & 0x2)
|
||||
return v >> 16;
|
||||
else
|
||||
return v & 0xffff;
|
||||
}
|
||||
|
||||
static uint32_t g364fb_ctrl_readl(void *opaque, target_phys_addr_t addr)
|
||||
static uint32_t g364fb_ctrl_readb(void *opaque, target_phys_addr_t addr)
|
||||
{
|
||||
uint32_t v;
|
||||
v = g364fb_ctrl_readb(opaque, addr);
|
||||
v |= g364fb_ctrl_readb(opaque, addr + 1) << 8;
|
||||
v |= g364fb_ctrl_readb(opaque, addr + 2) << 16;
|
||||
v |= g364fb_ctrl_readb(opaque, addr + 3) << 24;
|
||||
return v;
|
||||
uint32_t v = g364fb_ctrl_readl(opaque, addr & ~0x3);
|
||||
return (v >> (8 * (addr & 0x3))) & 0xff;
|
||||
}
|
||||
|
||||
static void g364fb_ctrl_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
|
||||
static void g364fb_update_depth(G364State *s)
|
||||
{
|
||||
G364State *s = opaque;
|
||||
const static int depths[8] = { 1, 2, 4, 8, 15, 16, 0 };
|
||||
s->depth = depths[(s->ctla & 0x00700000) >> 20];
|
||||
}
|
||||
|
||||
addr &= 0xffff;
|
||||
static void g364_invalidate_cursor_position(G364State *s)
|
||||
{
|
||||
int ymin, ymax, start, end, i;
|
||||
|
||||
#ifdef DEBUG_G364
|
||||
printf("g364fb/ctrl: write 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
|
||||
#endif
|
||||
/* invalidate only near the cursor */
|
||||
ymin = s->cursor_position & 0xfff;
|
||||
ymax = MIN(s->height, ymin + 64);
|
||||
start = ymin * ds_get_linesize(s->ds);
|
||||
end = (ymax + 1) * ds_get_linesize(s->ds);
|
||||
|
||||
if (addr < 0x0800) {
|
||||
/* color palette */
|
||||
int idx = addr >> 3;
|
||||
int c = addr & 7;
|
||||
if (c < 3)
|
||||
s->palette[idx][c] = (uint8_t)val;
|
||||
} else {
|
||||
switch (addr) {
|
||||
case REG_DISPLAYX:
|
||||
s->scr_width = (s->scr_width & 0xfffffc03) | (val << 2);
|
||||
break;
|
||||
case REG_DISPLAYX + 1:
|
||||
s->scr_width = (s->scr_width & 0xfffc03ff) | (val << 10);
|
||||
break;
|
||||
case REG_DISPLAYY:
|
||||
s->scr_height = (s->scr_height & 0xffffff80) | (val >> 1);
|
||||
break;
|
||||
case REG_DISPLAYY + 1:
|
||||
s->scr_height = (s->scr_height & 0xffff801f) | (val << 7);
|
||||
break;
|
||||
default:
|
||||
#ifdef DEBUG_G364
|
||||
printf("g364fb/ctrl: invalid write of 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
for (i = start; i < end; i += TARGET_PAGE_SIZE) {
|
||||
cpu_physical_memory_set_dirty(s->vram_offset + i);
|
||||
}
|
||||
s->graphic_mode = -1; /* force full update */
|
||||
}
|
||||
|
||||
static void g364fb_ctrl_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
|
||||
{
|
||||
g364fb_ctrl_writeb(opaque, addr, val & 0xff);
|
||||
g364fb_ctrl_writeb(opaque, addr + 1, (val >> 8) & 0xff);
|
||||
}
|
||||
|
||||
static void g364fb_ctrl_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
|
||||
{
|
||||
g364fb_ctrl_writeb(opaque, addr, val & 0xff);
|
||||
g364fb_ctrl_writeb(opaque, addr + 1, (val >> 8) & 0xff);
|
||||
g364fb_ctrl_writeb(opaque, addr + 2, (val >> 16) & 0xff);
|
||||
g364fb_ctrl_writeb(opaque, addr + 3, (val >> 24) & 0xff);
|
||||
G364State *s = opaque;
|
||||
|
||||
DPRINTF("write 0x%08x at [" TARGET_FMT_plx "]\n", val, addr);
|
||||
|
||||
if (addr >= REG_CLR_PAL && addr < REG_CLR_PAL + 0x800) {
|
||||
/* color palette */
|
||||
int idx = (addr - REG_CLR_PAL) >> 3;
|
||||
s->color_palette[idx][0] = (val >> 16) & 0xff;
|
||||
s->color_palette[idx][1] = (val >> 8) & 0xff;
|
||||
s->color_palette[idx][2] = val & 0xff;
|
||||
g364fb_invalidate_display(s);
|
||||
} else if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) {
|
||||
/* cursor pattern */
|
||||
int idx = (addr - REG_CURS_PAT) >> 3;
|
||||
s->cursor[idx] = val;
|
||||
g364fb_invalidate_display(s);
|
||||
} else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) {
|
||||
/* cursor palette */
|
||||
int idx = (addr - REG_CURS_PAL) >> 3;
|
||||
s->cursor_palette[idx][0] = (val >> 16) & 0xff;
|
||||
s->cursor_palette[idx][1] = (val >> 8) & 0xff;
|
||||
s->cursor_palette[idx][2] = val & 0xff;
|
||||
g364fb_invalidate_display(s);
|
||||
} else {
|
||||
switch (addr) {
|
||||
case REG_ID: /* Card identifier; read-only */
|
||||
case REG_BOOT: /* Boot timing */
|
||||
case 0x80108: /* Line timing: half sync */
|
||||
case 0x80110: /* Line timing: back porch */
|
||||
case 0x80120: /* Line timing: short display */
|
||||
case 0x80128: /* Frame timing: broad pulse */
|
||||
case 0x80130: /* Frame timing: v sync */
|
||||
case 0x80138: /* Frame timing: v preequalise */
|
||||
case 0x80140: /* Frame timing: v postequalise */
|
||||
case 0x80148: /* Frame timing: v blank */
|
||||
case 0x80158: /* Line timing: line time */
|
||||
case 0x80160: /* Frame store: line start */
|
||||
case 0x80168: /* vram cycle: mem init */
|
||||
case 0x80170: /* vram cycle: transfer delay */
|
||||
case 0x80200: /* vram cycle: mask register */
|
||||
/* ignore */
|
||||
break;
|
||||
case REG_TOP:
|
||||
s->top_of_screen = val;
|
||||
g364fb_invalidate_display(s);
|
||||
break;
|
||||
case REG_DISPLAY:
|
||||
s->width = val * 4;
|
||||
break;
|
||||
case REG_VDISPLAY:
|
||||
s->height = val / 2;
|
||||
break;
|
||||
case REG_CTLA:
|
||||
s->ctla = val;
|
||||
g364fb_update_depth(s);
|
||||
g364fb_invalidate_display(s);
|
||||
break;
|
||||
case REG_CURS_POS:
|
||||
g364_invalidate_cursor_position(s);
|
||||
s->cursor_position = val;
|
||||
g364_invalidate_cursor_position(s);
|
||||
break;
|
||||
case REG_RESET:
|
||||
g364fb_reset(s);
|
||||
break;
|
||||
default:
|
||||
BADF("invalid write of 0x%08x at [" TARGET_FMT_plx "]\n", val, addr);
|
||||
break;
|
||||
}
|
||||
}
|
||||
qemu_irq_lower(s->irq);
|
||||
}
|
||||
|
||||
static void g364fb_ctrl_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
|
||||
{
|
||||
uint32_t old_val = g364fb_ctrl_readl(opaque, addr & ~0x3);
|
||||
|
||||
if (addr & 0x2)
|
||||
val = (val << 16) | (old_val & 0x0000ffff);
|
||||
else
|
||||
val = val | (old_val & 0xffff0000);
|
||||
g364fb_ctrl_writel(opaque, addr & ~0x3, val);
|
||||
}
|
||||
|
||||
static void g364fb_ctrl_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
|
||||
{
|
||||
uint32_t old_val = g364fb_ctrl_readl(opaque, addr & ~0x3);
|
||||
|
||||
switch (addr & 3) {
|
||||
case 0:
|
||||
val = val | (old_val & 0xffffff00);
|
||||
break;
|
||||
case 1:
|
||||
val = (val << 8) | (old_val & 0xffff00ff);
|
||||
break;
|
||||
case 2:
|
||||
val = (val << 16) | (old_val & 0xff00ffff);
|
||||
break;
|
||||
case 3:
|
||||
val = (val << 24) | (old_val & 0x00ffffff);
|
||||
break;
|
||||
}
|
||||
g364fb_ctrl_writel(opaque, addr & ~0x3, val);
|
||||
}
|
||||
|
||||
static CPUReadMemoryFunc *g364fb_ctrl_read[3] = {
|
||||
|
|
@ -294,90 +535,84 @@ static CPUWriteMemoryFunc *g364fb_ctrl_write[3] = {
|
|||
g364fb_ctrl_writel,
|
||||
};
|
||||
|
||||
/* called for accesses to video ram */
|
||||
static uint32_t g364fb_mem_readb(void *opaque, target_phys_addr_t addr)
|
||||
static int g364fb_load(QEMUFile *f, void *opaque, int version_id)
|
||||
{
|
||||
G364State *s = opaque;
|
||||
unsigned int i, vram_size;
|
||||
|
||||
return s->vram_buffer[addr];
|
||||
if (version_id != 1)
|
||||
return -EINVAL;
|
||||
|
||||
vram_size = qemu_get_be32(f);
|
||||
if (vram_size < s->vram_size)
|
||||
return -EINVAL;
|
||||
qemu_get_buffer(f, s->vram, s->vram_size);
|
||||
for (i = 0; i < 256; i++)
|
||||
qemu_get_buffer(f, s->color_palette[i], 3);
|
||||
for (i = 0; i < 3; i++)
|
||||
qemu_get_buffer(f, s->cursor_palette[i], 3);
|
||||
qemu_get_buffer(f, (uint8_t *)s->cursor, sizeof(s->cursor));
|
||||
s->cursor_position = qemu_get_be32(f);
|
||||
s->ctla = qemu_get_be32(f);
|
||||
s->top_of_screen = qemu_get_be32(f);
|
||||
s->width = qemu_get_be32(f);
|
||||
s->height = qemu_get_be32(f);
|
||||
|
||||
/* force refresh */
|
||||
g364fb_update_depth(s);
|
||||
g364fb_invalidate_display(s);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static uint32_t g364fb_mem_readw(void *opaque, target_phys_addr_t addr)
|
||||
{
|
||||
uint32_t v;
|
||||
v = g364fb_mem_readb(opaque, addr);
|
||||
v |= g364fb_mem_readb(opaque, addr + 1) << 8;
|
||||
return v;
|
||||
}
|
||||
|
||||
static uint32_t g364fb_mem_readl(void *opaque, target_phys_addr_t addr)
|
||||
{
|
||||
uint32_t v;
|
||||
v = g364fb_mem_readb(opaque, addr);
|
||||
v |= g364fb_mem_readb(opaque, addr + 1) << 8;
|
||||
v |= g364fb_mem_readb(opaque, addr + 2) << 16;
|
||||
v |= g364fb_mem_readb(opaque, addr + 3) << 24;
|
||||
return v;
|
||||
}
|
||||
|
||||
static void g364fb_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
|
||||
static void g364fb_save(QEMUFile *f, void *opaque)
|
||||
{
|
||||
G364State *s = opaque;
|
||||
int i;
|
||||
|
||||
s->vram_buffer[addr] = val;
|
||||
qemu_put_be32(f, s->vram_size);
|
||||
qemu_put_buffer(f, s->vram, s->vram_size);
|
||||
for (i = 0; i < 256; i++)
|
||||
qemu_put_buffer(f, s->color_palette[i], 3);
|
||||
for (i = 0; i < 3; i++)
|
||||
qemu_put_buffer(f, s->cursor_palette[i], 3);
|
||||
qemu_put_buffer(f, (uint8_t *)s->cursor, sizeof(s->cursor));
|
||||
qemu_put_be32(f, s->cursor_position);
|
||||
qemu_put_be32(f, s->ctla);
|
||||
qemu_put_be32(f, s->top_of_screen);
|
||||
qemu_put_be32(f, s->width);
|
||||
qemu_put_be32(f, s->height);
|
||||
}
|
||||
|
||||
static void g364fb_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
|
||||
{
|
||||
g364fb_mem_writeb(opaque, addr, val & 0xff);
|
||||
g364fb_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
|
||||
}
|
||||
|
||||
static void g364fb_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
|
||||
{
|
||||
g364fb_mem_writeb(opaque, addr, val & 0xff);
|
||||
g364fb_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
|
||||
g364fb_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
|
||||
g364fb_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
|
||||
}
|
||||
|
||||
static CPUReadMemoryFunc *g364fb_mem_read[3] = {
|
||||
g364fb_mem_readb,
|
||||
g364fb_mem_readw,
|
||||
g364fb_mem_readl,
|
||||
};
|
||||
|
||||
static CPUWriteMemoryFunc *g364fb_mem_write[3] = {
|
||||
g364fb_mem_writeb,
|
||||
g364fb_mem_writew,
|
||||
g364fb_mem_writel,
|
||||
};
|
||||
|
||||
int g364fb_mm_init(int vram_size, int it_shift,
|
||||
target_phys_addr_t vram_base, target_phys_addr_t ctrl_base)
|
||||
int g364fb_mm_init(uint8_t *vram, ram_addr_t vram_offset,
|
||||
int vram_size, target_phys_addr_t vram_base,
|
||||
target_phys_addr_t ctrl_base, int it_shift,
|
||||
qemu_irq irq)
|
||||
{
|
||||
G364State *s;
|
||||
int io_vram, io_ctrl;
|
||||
int io_ctrl;
|
||||
|
||||
s = qemu_mallocz(sizeof(G364State));
|
||||
if (!s)
|
||||
return -1;
|
||||
|
||||
s->vram = vram;
|
||||
s->vram_offset = vram_offset;
|
||||
s->vram_size = vram_size;
|
||||
s->vram_buffer = qemu_mallocz(s->vram_size);
|
||||
s->irq = irq;
|
||||
|
||||
qemu_register_reset(g364fb_reset, s);
|
||||
register_savevm("g364fb", 0, 1, g364fb_save, g364fb_load, s);
|
||||
g364fb_reset(s);
|
||||
|
||||
s->ds = graphic_console_init(g364fb_update_display,
|
||||
g364fb_invalidate_display,
|
||||
g364fb_screen_dump, NULL, s);
|
||||
|
||||
io_vram = cpu_register_io_memory(0, g364fb_mem_read, g364fb_mem_write, s);
|
||||
cpu_register_physical_memory(vram_base, vram_size, io_vram);
|
||||
cpu_register_physical_memory(vram_base, s->vram_size, s->vram_offset);
|
||||
|
||||
io_ctrl = cpu_register_io_memory(0, g364fb_ctrl_read, g364fb_ctrl_write, s);
|
||||
cpu_register_physical_memory(ctrl_base, 0x10000, io_ctrl);
|
||||
cpu_register_physical_memory(ctrl_base, 0x200000, io_ctrl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,42 +0,0 @@
|
|||
/*
|
||||
* QEMU G364 framebuffer Emulator.
|
||||
*
|
||||
* Copyright (c) 2007 Hervé Poussineau
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
static void glue(g364fb_draw_graphic, BPP)(G364State *s, int full_update)
|
||||
{
|
||||
int i, j;
|
||||
int w_display;
|
||||
uint8_t *data_buffer;
|
||||
uint8_t *data_display, *dd;
|
||||
|
||||
data_buffer = s->vram_buffer;
|
||||
w_display = s->scr_width * PIXEL_WIDTH / 8;
|
||||
data_display = ds_get_data(s->ds);
|
||||
for(i = 0; i < s->scr_height; i++) {
|
||||
dd = data_display;
|
||||
for (j = 0; j < s->scr_width; j++, dd += PIXEL_WIDTH / 8, data_buffer++) {
|
||||
uint8_t index = *data_buffer;
|
||||
*((glue(glue(uint, PIXEL_WIDTH), _t) *)dd) = glue(rgb_to_pixel, BPP)(
|
||||
s->palette[index][0],
|
||||
s->palette[index][1],
|
||||
s->palette[index][2]);
|
||||
}
|
||||
data_display += ds_get_linesize(s->ds);
|
||||
}
|
||||
}
|
||||
|
|
@ -10,8 +10,10 @@ void *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
|
|||
void ds1225y_set_protection(void *opaque, int protection);
|
||||
|
||||
/* g364fb.c */
|
||||
int g364fb_mm_init(int vram_size, int it_shift,
|
||||
target_phys_addr_t vram_base, target_phys_addr_t ctrl_base);
|
||||
int g364fb_mm_init(uint8_t *vram, ram_addr_t vram_offset,
|
||||
int vram_size, target_phys_addr_t vram_base,
|
||||
target_phys_addr_t ctrl_base, int it_shift,
|
||||
qemu_irq irq);
|
||||
|
||||
/* mipsnet.c */
|
||||
void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
|
||||
|
|
|
|||
|
|
@ -201,7 +201,8 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
|
|||
/* Video card */
|
||||
switch (jazz_model) {
|
||||
case JAZZ_MAGNUM:
|
||||
g364fb_mm_init(vga_ram_size, 0, 0x40000000, 0x60000000);
|
||||
g364fb_mm_init(phys_ram_base + ram_size, ram_size, vga_ram_size,
|
||||
0x40000000, 0x60000000, 0, rc4030[3]);
|
||||
break;
|
||||
case JAZZ_PICA61:
|
||||
isa_vga_mm_init(phys_ram_base + ram_size, ram_size, vga_ram_size,
|
||||
|
|
|
|||
Loading…
Reference in a new issue