target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check
The ARM_FEATURE_PXN bit indicates whether the CPU supports the PXN bit in short-descriptor translation table format descriptors. This is indicated by ID_MMFR0.VMSA being at least 0b0100. Replace the feature bit with an ID register check, in line with our preference for ID register checks over feature bits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200910173855.4068-2-peter.maydell@linaro.org
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@ -1588,7 +1588,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
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}
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if (arm_feature(env, ARM_FEATURE_LPAE)) {
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set_feature(env, ARM_FEATURE_V7MP);
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set_feature(env, ARM_FEATURE_PXN);
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}
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if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
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set_feature(env, ARM_FEATURE_CBAR);
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@ -1772,6 +1772,15 @@ FIELD(ID_ISAR6, FHM, 8, 4)
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FIELD(ID_ISAR6, SB, 12, 4)
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FIELD(ID_ISAR6, SPECRES, 16, 4)
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FIELD(ID_MMFR0, VMSA, 0, 4)
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FIELD(ID_MMFR0, PMSA, 4, 4)
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FIELD(ID_MMFR0, OUTERSHR, 8, 4)
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FIELD(ID_MMFR0, SHARELVL, 12, 4)
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FIELD(ID_MMFR0, TCM, 16, 4)
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FIELD(ID_MMFR0, AUXREG, 20, 4)
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FIELD(ID_MMFR0, FCSE, 24, 4)
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FIELD(ID_MMFR0, INNERSHR, 28, 4)
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FIELD(ID_MMFR3, CMAINTVA, 0, 4)
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FIELD(ID_MMFR3, CMAINTSW, 4, 4)
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FIELD(ID_MMFR3, BPMAINT, 8, 4)
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@ -1949,7 +1958,6 @@ enum arm_features {
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ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
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ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
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ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
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ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
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ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
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ARM_FEATURE_V8,
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ARM_FEATURE_AARCH64, /* supports 64 bit mode */
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@ -3615,6 +3623,11 @@ static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
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return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;
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}
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static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id)
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{
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return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4;
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}
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static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
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{
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return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
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@ -10537,6 +10537,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
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target_ulong *page_size, ARMMMUFaultInfo *fi)
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{
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CPUState *cs = env_cpu(env);
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ARMCPU *cpu = env_archcpu(env);
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int level = 1;
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uint32_t table;
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uint32_t desc;
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@ -10563,7 +10564,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
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goto do_fault;
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}
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type = (desc & 3);
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if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
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if (type == 0 || (type == 3 && !cpu_isar_feature(aa32_pxn, cpu))) {
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/* Section translation fault, or attempt to use the encoding
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* which is Reserved on implementations without PXN.
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*/
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@ -10605,7 +10606,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
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pxn = desc & 1;
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ns = extract32(desc, 19, 1);
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} else {
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if (arm_feature(env, ARM_FEATURE_PXN)) {
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if (cpu_isar_feature(aa32_pxn, cpu)) {
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pxn = (desc >> 2) & 1;
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}
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ns = extract32(desc, 3, 1);
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