target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair
Implement support for nanoMIPS LLWP/SCWP instructions. Beside adding core functionality of these instructions, this patch adds support for availability control via configuration bit XNP. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Dimitrije Nikolic <dnikolic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
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@ -397,10 +397,13 @@ static int do_store_exclusive(CPUMIPSState *env)
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target_ulong addr;
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target_ulong addr;
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target_ulong page_addr;
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target_ulong page_addr;
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target_ulong val;
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target_ulong val;
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uint32_t val_wp = 0;
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uint32_t llnewval_wp = 0;
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int flags;
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int flags;
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int segv = 0;
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int segv = 0;
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int reg;
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int reg;
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int d;
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int d;
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int wp;
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addr = env->lladdr;
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addr = env->lladdr;
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page_addr = addr & TARGET_PAGE_MASK;
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page_addr = addr & TARGET_PAGE_MASK;
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@ -412,20 +415,32 @@ static int do_store_exclusive(CPUMIPSState *env)
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} else {
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} else {
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reg = env->llreg & 0x1f;
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reg = env->llreg & 0x1f;
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d = (env->llreg & 0x20) != 0;
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d = (env->llreg & 0x20) != 0;
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wp = (env->llreg & 0x40) != 0;
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if (!wp) {
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if (d) {
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if (d) {
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segv = get_user_s64(val, addr);
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segv = get_user_s64(val, addr);
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} else {
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} else {
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segv = get_user_s32(val, addr);
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segv = get_user_s32(val, addr);
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}
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}
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} else {
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segv = get_user_s32(val, addr);
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segv |= get_user_s32(val_wp, addr);
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llnewval_wp = env->llnewval_wp;
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}
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if (!segv) {
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if (!segv) {
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if (val != env->llval) {
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if (val != env->llval && val_wp == llnewval_wp) {
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env->active_tc.gpr[reg] = 0;
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env->active_tc.gpr[reg] = 0;
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} else {
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} else {
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if (!wp) {
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if (d) {
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if (d) {
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segv = put_user_u64(env->llnewval, addr);
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segv = put_user_u64(env->llnewval, addr);
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} else {
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} else {
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segv = put_user_u32(env->llnewval, addr);
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segv = put_user_u32(env->llnewval, addr);
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}
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}
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} else {
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segv = put_user_u32(env->llnewval, addr);
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segv |= put_user_u32(env->llnewval_wp, addr + 4);
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}
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if (!segv) {
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if (!segv) {
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env->active_tc.gpr[reg] = 1;
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env->active_tc.gpr[reg] = 1;
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}
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}
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@ -506,6 +506,8 @@ struct CPUMIPSState {
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uint64_t lladdr;
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uint64_t lladdr;
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target_ulong llval;
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target_ulong llval;
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target_ulong llnewval;
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target_ulong llnewval;
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uint64_t llval_wp;
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uint32_t llnewval_wp;
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target_ulong llreg;
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target_ulong llreg;
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uint64_t CP0_LLAddr_rw_bitmask;
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uint64_t CP0_LLAddr_rw_bitmask;
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int CP0_LLAddr_shift;
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int CP0_LLAddr_shift;
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@ -1916,6 +1916,18 @@ static inline void check_mvh(DisasContext *ctx)
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}
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}
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#endif
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#endif
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/*
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* This code generates a "reserved instruction" exception if the
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* Config5 XNP bit is set.
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*/
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static inline void check_xnp(DisasContext *ctx)
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{
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if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_XNP))) {
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generate_exception_end(ctx, EXCP_RI);
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}
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}
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/* Define small wrappers for gen_load_fpr* so that we have a uniform
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/* Define small wrappers for gen_load_fpr* so that we have a uniform
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calling interface for 32 and 64-bit FPRs. No sense in changing
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calling interface for 32 and 64-bit FPRs. No sense in changing
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all callers for gen_load_fpr32 when we need the CTX parameter for
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all callers for gen_load_fpr32 when we need the CTX parameter for
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@ -2362,6 +2374,31 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
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tcg_temp_free(t0);
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tcg_temp_free(t0);
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}
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}
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static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset,
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uint32_t reg1, uint32_t reg2)
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{
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TCGv taddr = tcg_temp_new();
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TCGv_i64 tval = tcg_temp_new_i64();
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TCGv tmp1 = tcg_temp_new();
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TCGv tmp2 = tcg_temp_new();
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gen_base_offset_addr(ctx, taddr, base, offset);
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tcg_gen_qemu_ld64(tval, taddr, ctx->mem_idx);
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#ifdef TARGET_WORDS_BIGENDIAN
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tcg_gen_extr_i64_tl(tmp2, tmp1, tval);
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#else
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tcg_gen_extr_i64_tl(tmp1, tmp2, tval);
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#endif
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gen_store_gpr(tmp1, reg1);
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tcg_temp_free(tmp1);
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gen_store_gpr(tmp2, reg2);
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tcg_temp_free(tmp2);
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tcg_gen_st_i64(tval, cpu_env, offsetof(CPUMIPSState, llval_wp));
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tcg_temp_free_i64(tval);
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tcg_gen_st_tl(taddr, cpu_env, offsetof(CPUMIPSState, lladdr));
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tcg_temp_free(taddr);
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}
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/* Store */
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/* Store */
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static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
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static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
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int base, int offset)
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int base, int offset)
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@ -2458,6 +2495,51 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
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tcg_temp_free(t0);
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tcg_temp_free(t0);
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}
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}
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static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
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uint32_t reg1, uint32_t reg2)
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{
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TCGv taddr = tcg_temp_local_new();
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TCGv lladdr = tcg_temp_local_new();
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TCGv_i64 tval = tcg_temp_new_i64();
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TCGv_i64 llval = tcg_temp_new_i64();
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TCGv_i64 val = tcg_temp_new_i64();
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TCGv tmp1 = tcg_temp_new();
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TCGv tmp2 = tcg_temp_new();
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TCGLabel *lab_fail = gen_new_label();
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TCGLabel *lab_done = gen_new_label();
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gen_base_offset_addr(ctx, taddr, base, offset);
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tcg_gen_ld_tl(lladdr, cpu_env, offsetof(CPUMIPSState, lladdr));
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tcg_gen_brcond_tl(TCG_COND_NE, taddr, lladdr, lab_fail);
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gen_load_gpr(tmp1, reg1);
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gen_load_gpr(tmp2, reg2);
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#ifdef TARGET_WORDS_BIGENDIAN
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tcg_gen_concat_tl_i64(tval, tmp2, tmp1);
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#else
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tcg_gen_concat_tl_i64(tval, tmp1, tmp2);
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#endif
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tcg_gen_ld_i64(llval, cpu_env, offsetof(CPUMIPSState, llval_wp));
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tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval,
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ctx->mem_idx, MO_64);
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if (reg1 != 0) {
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tcg_gen_movi_tl(cpu_gpr[reg1], 1);
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}
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tcg_gen_brcond_i64(TCG_COND_EQ, val, llval, lab_done);
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gen_set_label(lab_fail);
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if (reg1 != 0) {
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tcg_gen_movi_tl(cpu_gpr[reg1], 0);
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}
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gen_set_label(lab_done);
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tcg_gen_movi_tl(lladdr, -1);
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tcg_gen_st_tl(lladdr, cpu_env, offsetof(CPUMIPSState, lladdr));
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}
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/* Load and store */
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/* Load and store */
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static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
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static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
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TCGv t0)
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TCGv t0)
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@ -18120,6 +18202,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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gen_ld(ctx, OPC_LL, rt, rs, s);
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gen_ld(ctx, OPC_LL, rt, rs, s);
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break;
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break;
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case NM_LLWP:
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case NM_LLWP:
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check_xnp(ctx);
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gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
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break;
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break;
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}
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}
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break;
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break;
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@ -18129,6 +18213,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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gen_st_cond(ctx, OPC_SC, rt, rs, s);
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gen_st_cond(ctx, OPC_SC, rt, rs, s);
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break;
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break;
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case NM_SCWP:
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case NM_SCWP:
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check_xnp(ctx);
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gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
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break;
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break;
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}
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}
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break;
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break;
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