tests/tcg: Add arm and aarch64 pc alignment tests
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -8,8 +8,8 @@ VPATH += $(ARM_SRC)
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AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64
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AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64
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VPATH += $(AARCH64_SRC)
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VPATH += $(AARCH64_SRC)
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# Float-convert Tests
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# Base architecture tests
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AARCH64_TESTS=fcvt
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AARCH64_TESTS=fcvt pcalign-a64
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fcvt: LDFLAGS+=-lm
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fcvt: LDFLAGS+=-lm
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37
tests/tcg/aarch64/pcalign-a64.c
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37
tests/tcg/aarch64/pcalign-a64.c
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@ -0,0 +1,37 @@
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/* Test PC misalignment exception */
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#include <assert.h>
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#include <signal.h>
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#include <stdlib.h>
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#include <stdio.h>
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static void *expected;
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static void sigbus(int sig, siginfo_t *info, void *vuc)
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{
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assert(info->si_code == BUS_ADRALN);
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assert(info->si_addr == expected);
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exit(EXIT_SUCCESS);
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}
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int main()
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{
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void *tmp;
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struct sigaction sa = {
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.sa_sigaction = sigbus,
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.sa_flags = SA_SIGINFO
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};
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if (sigaction(SIGBUS, &sa, NULL) < 0) {
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perror("sigaction");
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return EXIT_FAILURE;
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}
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asm volatile("adr %0, 1f + 1\n\t"
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"str %0, %1\n\t"
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"br %0\n"
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"1:"
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: "=&r"(tmp), "=m"(expected));
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abort();
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}
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@ -29,6 +29,10 @@ run-fcvt: fcvt
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$(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)")
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$(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)")
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$(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref)
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$(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref)
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# PC alignment test
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ARM_TESTS += pcalign-a32
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pcalign-a32: CFLAGS+=-marm
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ifeq ($(CONFIG_ARM_COMPATIBLE_SEMIHOSTING),y)
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ifeq ($(CONFIG_ARM_COMPATIBLE_SEMIHOSTING),y)
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# Semihosting smoke test for linux-user
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# Semihosting smoke test for linux-user
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46
tests/tcg/arm/pcalign-a32.c
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46
tests/tcg/arm/pcalign-a32.c
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@ -0,0 +1,46 @@
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/* Test PC misalignment exception */
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#ifdef __thumb__
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#error "This test must be compiled for ARM"
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#endif
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#include <assert.h>
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#include <signal.h>
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#include <stdlib.h>
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#include <stdio.h>
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static void *expected;
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static void sigbus(int sig, siginfo_t *info, void *vuc)
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{
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assert(info->si_code == BUS_ADRALN);
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assert(info->si_addr == expected);
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exit(EXIT_SUCCESS);
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}
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int main()
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{
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void *tmp;
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struct sigaction sa = {
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.sa_sigaction = sigbus,
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.sa_flags = SA_SIGINFO
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};
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if (sigaction(SIGBUS, &sa, NULL) < 0) {
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perror("sigaction");
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return EXIT_FAILURE;
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}
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asm volatile("adr %0, 1f + 2\n\t"
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"str %0, %1\n\t"
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"bx %0\n"
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"1:"
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: "=&r"(tmp), "=m"(expected));
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/*
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* From v8, it is CONSTRAINED UNPREDICTABLE whether BXWritePC aligns
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* the address or not. If so, we can legitimately fall through.
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*/
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return EXIT_SUCCESS;
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}
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