target-arm queue:
* implement WFE as yield (improves performance with emulated SMP) * fixes to avoid undefined behaviour shifting left into sign bit * libvixl format string fixes for 32 bit hosts * fix build error when intptr_t and tcg_target_long are different sizes (eg x32) * implement PMCCNTR register * fix incorrect setting of E bit in CPSR (broke booting under KVM on ARM) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABCAAGBQJTHdS1AAoJEDwlJe0UNgze0B8P/3DkFSe5hKQhU4mcqsQ8/bXJ ub75hyA/vm1anZIsrKQkOz0+ySNjphyhGtQVDCERc/r2hhwYl7v+9KZ/LS8LECYD Dl0Rf7woTYNwJKwyKuXbFjHkl443gDa5FS0HR1QD1t3gp1T/AMkgq7XsjUOlx6Up h14m0/3NQB3fgU5VmqYeUC4wVuH6SVhPo9CSVH864HGX4lBL30zfMoJjluZCQ6Y9 Qo3FOPXT+rWmLmiiFgbEVHs96mfN05ooiIbpISCKSKL/9LujoeX6PV2qX6KFyk3T zhWY4X65Gz6PqW1LZR9DUkl4NWxIjdYVS2DE2cOgQJLz6guy6JEfLoWechHyzBXa w4evOmoexaVlY713joMtDceRrIeAzPLS69rS1HuRj85MikFpqNrY4g2lEqGgCaWH oQ3W8UpcEMfvBIKXyAF8i8UJNH8q5YkI+z4KT2TOX3y+KiVcwixDuWizsjW7uLUN zdLaYWXYRLa026b37AY0Y0k/K2kQt1yXemI5hk4P4jCQM/2/hireO5Z9TYBpD8ym Igsq0ljH7gpyExhXsyvL73ZmFOTmdO1RwU5ybSR8ZzfpAT6W+e1acQOZ/8WyWVcz gsrwVeuTlK04nte9fpmrN54MeEHr3Jn2K4bsOfeKFRPD/pvORRAzLIHQJO/SPXoA Cmn/627VVNTnpBhtlSlc =SHmz -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140310' into staging target-arm queue: * implement WFE as yield (improves performance with emulated SMP) * fixes to avoid undefined behaviour shifting left into sign bit * libvixl format string fixes for 32 bit hosts * fix build error when intptr_t and tcg_target_long are different sizes (eg x32) * implement PMCCNTR register * fix incorrect setting of E bit in CPSR (broke booting under KVM on ARM) # gpg: Signature made Mon 10 Mar 2014 15:05:25 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140310: target-arm: Implement WFE as a yield operation hw/arm/musicpal: Avoid shifting left into sign bit hw/ssi/xilinx_spips.c: Avoid shifting left into sign bit hw/arm/omap1.c: Avoid shifting left into sign bit pxa2xx: Don't shift into sign bit libvixl: Fix format strings for several int64_t values target-arm: Fix intptr_t vs tcg_target_long target-arm: Implements the ARM PMCCNTR register target-arm: Fix incorrect setting of E bit in CPSR Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
0ca540dbae
|
@ -1342,7 +1342,7 @@ int Disassembler::SubstituteImmediateField(Instruction* instr,
|
|||
ASSERT(format[5] == 'L');
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||||
AppendToOutput("#0x%" PRIx64, instr->ImmMoveWide());
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if (instr->ShiftMoveWide() > 0) {
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AppendToOutput(", lsl #%d", 16 * instr->ShiftMoveWide());
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AppendToOutput(", lsl #%" PRId64, 16 * instr->ShiftMoveWide());
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}
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}
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return 8;
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|
@ -1391,7 +1391,7 @@ int Disassembler::SubstituteImmediateField(Instruction* instr,
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}
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case 'F': { // IFPSingle, IFPDouble or IFPFBits.
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if (format[3] == 'F') { // IFPFbits.
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AppendToOutput("#%d", 64 - instr->FPScale());
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AppendToOutput("#%" PRId64, 64 - instr->FPScale());
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return 8;
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} else {
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AppendToOutput("#0x%" PRIx64 " (%.4f)", instr->ImmFP(),
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|
@ -1412,23 +1412,23 @@ int Disassembler::SubstituteImmediateField(Instruction* instr,
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return 5;
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}
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case 'P': { // IP - Conditional compare.
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AppendToOutput("#%d", instr->ImmCondCmp());
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AppendToOutput("#%" PRId64, instr->ImmCondCmp());
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return 2;
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}
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case 'B': { // Bitfields.
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return SubstituteBitfieldImmediateField(instr, format);
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}
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case 'E': { // IExtract.
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AppendToOutput("#%d", instr->ImmS());
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AppendToOutput("#%" PRId64, instr->ImmS());
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return 8;
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}
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case 'S': { // IS - Test and branch bit.
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AppendToOutput("#%d", (instr->ImmTestBranchBit5() << 5) |
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AppendToOutput("#%" PRId64, (instr->ImmTestBranchBit5() << 5) |
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instr->ImmTestBranchBit40());
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return 2;
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}
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case 'D': { // IDebug - HLT and BRK instructions.
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AppendToOutput("#0x%x", instr->ImmException());
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AppendToOutput("#0x%" PRIx64, instr->ImmException());
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return 6;
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}
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default: {
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|
@ -1598,12 +1598,12 @@ int Disassembler::SubstituteExtendField(Instruction* instr,
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(((instr->ExtendMode() == UXTW) && (instr->SixtyFourBits() == 0)) ||
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(instr->ExtendMode() == UXTX))) {
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if (instr->ImmExtendShift() > 0) {
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AppendToOutput(", lsl #%d", instr->ImmExtendShift());
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AppendToOutput(", lsl #%" PRId64, instr->ImmExtendShift());
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}
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} else {
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AppendToOutput(", %s", extend_mode[instr->ExtendMode()]);
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if (instr->ImmExtendShift() > 0) {
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AppendToOutput(" #%d", instr->ImmExtendShift());
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AppendToOutput(" #%" PRId64, instr->ImmExtendShift());
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}
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}
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return 3;
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|
@ -1632,7 +1632,7 @@ int Disassembler::SubstituteLSRegOffsetField(Instruction* instr,
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if (!((ext == UXTX) && (shift == 0))) {
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AppendToOutput(", %s", extend_mode[ext]);
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if (shift != 0) {
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AppendToOutput(" #%d", instr->SizeLS());
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AppendToOutput(" #%" PRId64, instr->SizeLS());
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}
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}
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return 9;
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|
|
|
@ -110,10 +110,10 @@
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#define MP_PHY_88E3015 0x01410E20
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/* TX descriptor status */
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#define MP_ETH_TX_OWN (1 << 31)
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#define MP_ETH_TX_OWN (1U << 31)
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/* RX descriptor status */
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#define MP_ETH_RX_OWN (1 << 31)
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#define MP_ETH_RX_OWN (1U << 31)
|
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|
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/* Interrupt cause/mask bits */
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#define MP_ETH_IRQ_RX_BIT 0
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|
|
|
@ -809,22 +809,26 @@ static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s,
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uint32_t diff, uint32_t value)
|
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{
|
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if (s->compat1509) {
|
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if (diff & (1 << 31)) /* MCBSP3_CLK_HIZ_DI */
|
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omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"),
|
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(value >> 31) & 1);
|
||||
if (diff & (1 << 1)) /* CLK32K */
|
||||
omap_clk_onoff(omap_findclk(s, "clk32k_out"),
|
||||
(~value >> 1) & 1);
|
||||
if (diff & (1U << 31)) {
|
||||
/* MCBSP3_CLK_HIZ_DI */
|
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omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"), (value >> 31) & 1);
|
||||
}
|
||||
if (diff & (1 << 1)) {
|
||||
/* CLK32K */
|
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omap_clk_onoff(omap_findclk(s, "clk32k_out"), (~value >> 1) & 1);
|
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}
|
||||
}
|
||||
}
|
||||
|
||||
static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
|
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uint32_t diff, uint32_t value)
|
||||
{
|
||||
if (diff & (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */
|
||||
if (diff & (1U << 31)) {
|
||||
/* CONF_MOD_UART3_CLK_MODE_R */
|
||||
omap_clk_reparent(omap_findclk(s, "uart3_ck"),
|
||||
omap_findclk(s, ((value >> 31) & 1) ?
|
||||
"ck_48m" : "armper_ck"));
|
||||
}
|
||||
if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */
|
||||
omap_clk_reparent(omap_findclk(s, "uart2_ck"),
|
||||
omap_findclk(s, ((value >> 30) & 1) ?
|
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|
|
|
@ -259,7 +259,7 @@ static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
|||
|
||||
case 1:
|
||||
/* Idle */
|
||||
if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */
|
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if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */
|
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cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
|
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break;
|
||||
}
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|
@ -496,7 +496,7 @@ typedef struct {
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#define SSCR0_SSE (1 << 7)
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#define SSCR0_RIM (1 << 22)
|
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#define SSCR0_TIM (1 << 23)
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#define SSCR0_MOD (1 << 31)
|
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#define SSCR0_MOD (1U << 31)
|
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#define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
|
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#define SSCR1_RIE (1 << 0)
|
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#define SSCR1_TIE (1 << 1)
|
||||
|
@ -1006,7 +1006,7 @@ static void pxa2xx_rtc_write(void *opaque, hwaddr addr,
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|
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switch (addr) {
|
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case RTTR:
|
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if (!(s->rttr & (1 << 31))) {
|
||||
if (!(s->rttr & (1U << 31))) {
|
||||
pxa2xx_rtc_hzupdate(s);
|
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s->rttr = value;
|
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pxa2xx_rtc_alarm_update(s, s->rtsr);
|
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|
|
|
@ -110,7 +110,7 @@ static void pxa2xx_gpio_set(void *opaque, int line, int level)
|
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}
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bank = line >> 5;
|
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mask = 1 << (line & 31);
|
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mask = 1U << (line & 31);
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|
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if (level) {
|
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s->status[bank] |= s->rising[bank] & mask &
|
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|
|
|
@ -105,7 +105,7 @@ static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) {
|
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|
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for (i = PXA2XX_PIC_SRCS - 1; i >= 0; i --) {
|
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irq = s->priority[i] & 0x3f;
|
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if ((s->priority[i] & (1 << 31)) && irq < PXA2XX_PIC_SRCS) {
|
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if ((s->priority[i] & (1U << 31)) && irq < PXA2XX_PIC_SRCS) {
|
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/* Source peripheral ID is valid. */
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bit = 1 << (irq & 31);
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int_set = (irq >= 32);
|
||||
|
@ -119,7 +119,7 @@ static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) {
|
|||
if (mask[int_set] & bit & ~s->is_fiq[int_set]) {
|
||||
/* IRQ asserted */
|
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ichp &= 0x0000ffff;
|
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ichp |= (1 << 31) | (irq << 16);
|
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ichp |= (1U << 31) | (irq << 16);
|
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}
|
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}
|
||||
}
|
||||
|
|
|
@ -43,7 +43,7 @@
|
|||
|
||||
/* config register */
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#define R_CONFIG (0x00 / 4)
|
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#define IFMODE (1 << 31)
|
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#define IFMODE (1U << 31)
|
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#define ENDIAN (1 << 26)
|
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#define MODEFAIL_GEN_EN (1 << 17)
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#define MAN_START_COM (1 << 16)
|
||||
|
@ -87,7 +87,7 @@
|
|||
|
||||
#define R_LQSPI_CFG (0xa0 / 4)
|
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#define R_LQSPI_CFG_RESET 0x03A002EB
|
||||
#define LQSPI_CFG_LQ_MODE (1 << 31)
|
||||
#define LQSPI_CFG_LQ_MODE (1U << 31)
|
||||
#define LQSPI_CFG_TWO_MEM (1 << 30)
|
||||
#define LQSPI_CFG_SEP_BUS (1 << 30)
|
||||
#define LQSPI_CFG_U_PAGE (1 << 28)
|
||||
|
|
|
@ -59,6 +59,7 @@ typedef uint64_t target_ulong;
|
|||
#define EXCP_HLT 0x10001 /* hlt instruction reached */
|
||||
#define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
|
||||
#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
|
||||
#define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */
|
||||
|
||||
#define TB_JMP_CACHE_BITS 12
|
||||
#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
|
||||
|
|
|
@ -222,6 +222,10 @@ typedef struct CPUARMState {
|
|||
uint64_t dbgbcr[16]; /* breakpoint control registers */
|
||||
uint64_t dbgwvr[16]; /* watchpoint value registers */
|
||||
uint64_t dbgwcr[16]; /* watchpoint control registers */
|
||||
/* If the counter is enabled, this stores the last time the counter
|
||||
* was reset. Otherwise it stores the counter value
|
||||
*/
|
||||
uint32_t c15_ccnt;
|
||||
} cp15;
|
||||
|
||||
struct {
|
||||
|
|
|
@ -13,6 +13,11 @@ static inline int get_phys_addr(CPUARMState *env, uint32_t address,
|
|||
int access_type, int is_user,
|
||||
hwaddr *phys_ptr, int *prot,
|
||||
target_ulong *page_size);
|
||||
|
||||
/* Definitions for the PMCCNTR and PMCR registers */
|
||||
#define PMCRD 0x8
|
||||
#define PMCRC 0x4
|
||||
#define PMCRE 0x1
|
||||
#endif
|
||||
|
||||
static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
|
||||
|
@ -478,13 +483,84 @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
|
|||
return CP_ACCESS_OK;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
uint64_t value)
|
||||
{
|
||||
/* Don't computer the number of ticks in user mode */
|
||||
uint32_t temp_ticks;
|
||||
|
||||
temp_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
|
||||
get_ticks_per_sec() / 1000000;
|
||||
|
||||
if (env->cp15.c9_pmcr & PMCRE) {
|
||||
/* If the counter is enabled */
|
||||
if (env->cp15.c9_pmcr & PMCRD) {
|
||||
/* Increment once every 64 processor clock cycles */
|
||||
env->cp15.c15_ccnt = (temp_ticks/64) - env->cp15.c15_ccnt;
|
||||
} else {
|
||||
env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
|
||||
}
|
||||
}
|
||||
|
||||
if (value & PMCRC) {
|
||||
/* The counter has been reset */
|
||||
env->cp15.c15_ccnt = 0;
|
||||
}
|
||||
|
||||
/* only the DP, X, D and E bits are writable */
|
||||
env->cp15.c9_pmcr &= ~0x39;
|
||||
env->cp15.c9_pmcr |= (value & 0x39);
|
||||
|
||||
if (env->cp15.c9_pmcr & PMCRE) {
|
||||
if (env->cp15.c9_pmcr & PMCRD) {
|
||||
/* Increment once every 64 processor clock cycles */
|
||||
temp_ticks /= 64;
|
||||
}
|
||||
env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
|
||||
}
|
||||
}
|
||||
|
||||
static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
|
||||
{
|
||||
uint32_t total_ticks;
|
||||
|
||||
if (!(env->cp15.c9_pmcr & PMCRE)) {
|
||||
/* Counter is disabled, do not change value */
|
||||
return env->cp15.c15_ccnt;
|
||||
}
|
||||
|
||||
total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
|
||||
get_ticks_per_sec() / 1000000;
|
||||
|
||||
if (env->cp15.c9_pmcr & PMCRD) {
|
||||
/* Increment once every 64 processor clock cycles */
|
||||
total_ticks /= 64;
|
||||
}
|
||||
return total_ticks - env->cp15.c15_ccnt;
|
||||
}
|
||||
|
||||
static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
uint64_t value)
|
||||
{
|
||||
uint32_t total_ticks;
|
||||
|
||||
if (!(env->cp15.c9_pmcr & PMCRE)) {
|
||||
/* Counter is disabled, set the absolute value */
|
||||
env->cp15.c15_ccnt = value;
|
||||
return;
|
||||
}
|
||||
|
||||
total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
|
||||
get_ticks_per_sec() / 1000000;
|
||||
|
||||
if (env->cp15.c9_pmcr & PMCRD) {
|
||||
/* Increment once every 64 processor clock cycles */
|
||||
total_ticks /= 64;
|
||||
}
|
||||
env->cp15.c15_ccnt = total_ticks - value;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
uint64_t value)
|
||||
|
@ -604,10 +680,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
|
|||
{ .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
|
||||
.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
|
||||
.accessfn = pmreg_access },
|
||||
/* Unimplemented, RAZ/WI. */
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
{ .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
|
||||
.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
|
||||
.access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
|
||||
.readfn = pmccntr_read, .writefn = pmccntr_write,
|
||||
.accessfn = pmreg_access },
|
||||
#endif
|
||||
{ .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
|
||||
.access = PL0_RW,
|
||||
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
|
||||
|
@ -1873,8 +1951,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
|
|||
}
|
||||
if (arm_feature(env, ARM_FEATURE_V7)) {
|
||||
/* v7 performance monitor control register: same implementor
|
||||
* field as main ID register, and we implement no event counters.
|
||||
* field as main ID register, and we implement only the cycle
|
||||
* count register.
|
||||
*/
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
ARMCPRegInfo pmcr = {
|
||||
.name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
|
||||
.access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
|
||||
|
@ -1882,12 +1962,13 @@ void register_cp_regs_for_features(ARMCPU *cpu)
|
|||
.accessfn = pmreg_access, .writefn = pmcr_write,
|
||||
.raw_writefn = raw_write,
|
||||
};
|
||||
define_one_arm_cp_reg(cpu, &pmcr);
|
||||
#endif
|
||||
ARMCPRegInfo clidr = {
|
||||
.name = "CLIDR", .state = ARM_CP_STATE_BOTH,
|
||||
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
|
||||
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
|
||||
};
|
||||
define_one_arm_cp_reg(cpu, &pmcr);
|
||||
define_one_arm_cp_reg(cpu, &clidr);
|
||||
define_arm_cp_regs(cpu, v7_cp_reginfo);
|
||||
} else {
|
||||
|
@ -2478,7 +2559,7 @@ uint32_t cpsr_read(CPUARMState *env)
|
|||
(env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
|
||||
| (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
|
||||
| ((env->condexec_bits & 0xfc) << 8)
|
||||
| (env->GE << 16) | env->daif;
|
||||
| (env->GE << 16) | (env->daif & CPSR_AIF);
|
||||
}
|
||||
|
||||
void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
|
||||
|
|
|
@ -50,6 +50,7 @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE,
|
|||
i32, i32, i32, i32)
|
||||
DEF_HELPER_2(exception, void, env, i32)
|
||||
DEF_HELPER_1(wfi, void, env)
|
||||
DEF_HELPER_1(wfe, void, env)
|
||||
|
||||
DEF_HELPER_3(cpsr_write, void, env, i32, i32)
|
||||
DEF_HELPER_1(cpsr_read, i32, env)
|
||||
|
|
|
@ -225,6 +225,15 @@ void HELPER(wfi)(CPUARMState *env)
|
|||
cpu_loop_exit(env);
|
||||
}
|
||||
|
||||
void HELPER(wfe)(CPUARMState *env)
|
||||
{
|
||||
/* Don't actually halt the CPU, just yield back to top
|
||||
* level loop
|
||||
*/
|
||||
env->exception_index = EXCP_YIELD;
|
||||
cpu_loop_exit(env);
|
||||
}
|
||||
|
||||
void HELPER(exception)(CPUARMState *env, uint32_t excp)
|
||||
{
|
||||
env->exception_index = excp;
|
||||
|
|
|
@ -210,7 +210,7 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
|
|||
if (use_goto_tb(s, n, dest)) {
|
||||
tcg_gen_goto_tb(n);
|
||||
gen_a64_set_pc_im(dest);
|
||||
tcg_gen_exit_tb((tcg_target_long)tb + n);
|
||||
tcg_gen_exit_tb((intptr_t)tb + n);
|
||||
s->is_jmp = DISAS_TB_JUMP;
|
||||
} else {
|
||||
gen_a64_set_pc_im(dest);
|
||||
|
|
|
@ -3939,6 +3939,9 @@ static void gen_nop_hint(DisasContext *s, int val)
|
|||
s->is_jmp = DISAS_WFI;
|
||||
break;
|
||||
case 2: /* wfe */
|
||||
gen_set_pc_im(s, s->pc);
|
||||
s->is_jmp = DISAS_WFE;
|
||||
break;
|
||||
case 4: /* sev */
|
||||
case 5: /* sevl */
|
||||
/* TODO: Implement SEV, SEVL and WFE. May help SMP performance. */
|
||||
|
@ -10857,6 +10860,9 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
|
|||
case DISAS_WFI:
|
||||
gen_helper_wfi(cpu_env);
|
||||
break;
|
||||
case DISAS_WFE:
|
||||
gen_helper_wfe(cpu_env);
|
||||
break;
|
||||
case DISAS_SWI:
|
||||
gen_exception(EXCP_SWI);
|
||||
break;
|
||||
|
|
|
@ -44,6 +44,8 @@ extern TCGv_ptr cpu_env;
|
|||
* emitting unreachable code at the end of the TB in the A64 decoder
|
||||
*/
|
||||
#define DISAS_EXC 6
|
||||
/* WFE */
|
||||
#define DISAS_WFE 7
|
||||
|
||||
#ifdef TARGET_AARCH64
|
||||
void a64_translate_init(void);
|
||||
|
|
Loading…
Reference in a new issue