ARM: Samsung exynos4210-based boards emulation
Add initial support of NURI and SMDKC210 boards Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Evgeny Voevodin
Peter Maydell
parent
8e03cf1eeb
commit
0caa711335
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@ -344,7 +344,8 @@ obj-arm-y = integratorcp.o versatilepb.o arm_pic.o arm_timer.o
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obj-arm-y += arm_boot.o pl011.o pl031.o pl050.o pl080.o pl110.o pl181.o pl190.o
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obj-arm-y += versatile_pci.o
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obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
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obj-arm-y += exynos4210_gic.o exynos4210_combiner.o
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obj-arm-y += exynos4210_gic.o exynos4210_combiner.o exynos4210.o
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obj-arm-y += exynos4_boards.o
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obj-arm-y += arm_l2x0.o
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obj-arm-y += arm_mptimer.o
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obj-arm-y += armv7m.o armv7m_nvic.o stellaris.o pl022.o stellaris_enet.o
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191
hw/exynos4210.c
Normal file
191
hw/exynos4210.c
Normal file
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@ -0,0 +1,191 @@
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/*
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* Samsung exynos4210 SoC emulation
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
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* Maksim Kozlov <m.kozlov@samsung.com>
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* Evgeny Voevodin <e.voevodin@samsung.com>
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* Igor Mitsyanko <i.mitsyanko@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include "boards.h"
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#include "sysemu.h"
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#include "sysbus.h"
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#include "arm-misc.h"
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#include "exynos4210.h"
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#define EXYNOS4210_CHIPID_ADDR 0x10000000
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/* External GIC */
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#define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000
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#define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000
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/* Combiner */
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#define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000
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#define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000
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static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
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0x09, 0x00, 0x00, 0x00 };
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Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
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unsigned long ram_size)
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{
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qemu_irq cpu_irq[4];
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int n;
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Exynos4210State *s = g_new(Exynos4210State, 1);
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qemu_irq *irqp;
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qemu_irq gate_irq[EXYNOS4210_IRQ_GATE_NINPUTS];
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unsigned long mem_size;
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DeviceState *dev;
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SysBusDevice *busdev;
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for (n = 0; n < EXYNOS4210_NCPUS; n++) {
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s->env[n] = cpu_init("cortex-a9");
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if (!s->env[n]) {
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fprintf(stderr, "Unable to find CPU %d definition\n", n);
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exit(1);
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}
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/* Create PIC controller for each processor instance */
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irqp = arm_pic_init_cpu(s->env[n]);
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/*
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* Get GICs gpio_in cpu_irq to connect a combiner to them later.
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* Use only IRQ for a while.
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*/
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cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
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}
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/*** IRQs ***/
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s->irq_table = exynos4210_init_irq(&s->irqs);
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/* IRQ Gate */
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dev = qdev_create(NULL, "exynos4210.irq_gate");
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qdev_init_nofail(dev);
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/* Get IRQ Gate input in gate_irq */
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for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
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gate_irq[n] = qdev_get_gpio_in(dev, n);
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}
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busdev = sysbus_from_qdev(dev);
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/* Connect IRQ Gate output to cpu_irq */
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for (n = 0; n < EXYNOS4210_NCPUS; n++) {
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sysbus_connect_irq(busdev, n, cpu_irq[n]);
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}
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/* Private memory region and Internal GIC */
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dev = qdev_create(NULL, "a9mpcore_priv");
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qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
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qdev_init_nofail(dev);
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busdev = sysbus_from_qdev(dev);
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sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
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for (n = 0; n < EXYNOS4210_NCPUS; n++) {
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sysbus_connect_irq(busdev, n, gate_irq[n * 2]);
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}
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for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
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s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
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}
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/* Cache controller */
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sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
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/* External GIC */
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dev = qdev_create(NULL, "exynos4210.gic");
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qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
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qdev_init_nofail(dev);
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busdev = sysbus_from_qdev(dev);
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/* Map CPU interface */
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sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
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/* Map Distributer interface */
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sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
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for (n = 0; n < EXYNOS4210_NCPUS; n++) {
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sysbus_connect_irq(busdev, n, gate_irq[n * 2 + 1]);
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}
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for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
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s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
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}
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/* Internal Interrupt Combiner */
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dev = qdev_create(NULL, "exynos4210.combiner");
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qdev_init_nofail(dev);
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busdev = sysbus_from_qdev(dev);
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for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
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sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
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}
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exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
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sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
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/* External Interrupt Combiner */
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dev = qdev_create(NULL, "exynos4210.combiner");
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qdev_prop_set_uint32(dev, "external", 1);
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qdev_init_nofail(dev);
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busdev = sysbus_from_qdev(dev);
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for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
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sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
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}
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exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
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sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
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/* Initialize board IRQs. */
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exynos4210_init_board_irqs(&s->irqs);
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/*** Memory ***/
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/* Chip-ID and OMR */
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memory_region_init_ram_ptr(&s->chipid_mem, "exynos4210.chipid",
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sizeof(chipid_and_omr), chipid_and_omr);
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memory_region_set_readonly(&s->chipid_mem, true);
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memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR,
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&s->chipid_mem);
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/* Internal ROM */
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memory_region_init_ram(&s->irom_mem, "exynos4210.irom",
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EXYNOS4210_IROM_SIZE);
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memory_region_set_readonly(&s->irom_mem, true);
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memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR,
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&s->irom_mem);
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/* mirror of iROM */
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memory_region_init_alias(&s->irom_alias_mem, "exynos4210.irom_alias",
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&s->irom_mem,
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EXYNOS4210_IROM_BASE_ADDR,
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EXYNOS4210_IROM_SIZE);
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memory_region_set_readonly(&s->irom_alias_mem, true);
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memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR,
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&s->irom_alias_mem);
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/* Internal RAM */
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memory_region_init_ram(&s->iram_mem, "exynos4210.iram",
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EXYNOS4210_IRAM_SIZE);
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vmstate_register_ram_global(&s->iram_mem);
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memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
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&s->iram_mem);
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/* DRAM */
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mem_size = ram_size;
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if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
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memory_region_init_ram(&s->dram1_mem, "exynos4210.dram1",
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mem_size - EXYNOS4210_DRAM_MAX_SIZE);
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vmstate_register_ram_global(&s->dram1_mem);
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memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
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&s->dram1_mem);
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mem_size = EXYNOS4210_DRAM_MAX_SIZE;
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}
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memory_region_init_ram(&s->dram0_mem, "exynos4210.dram0", mem_size);
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vmstate_register_ram_global(&s->dram0_mem);
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memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
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&s->dram0_mem);
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return s;
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}
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@ -31,6 +31,28 @@
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#define EXYNOS4210_NCPUS 2
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#define EXYNOS4210_DRAM0_BASE_ADDR 0x40000000
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#define EXYNOS4210_DRAM1_BASE_ADDR 0xa0000000
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#define EXYNOS4210_DRAM_MAX_SIZE 0x60000000 /* 1.5 GB */
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#define EXYNOS4210_IROM_BASE_ADDR 0x00000000
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#define EXYNOS4210_IROM_SIZE 0x00010000 /* 64 KB */
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#define EXYNOS4210_IROM_MIRROR_BASE_ADDR 0x02000000
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#define EXYNOS4210_IROM_MIRROR_SIZE 0x00010000 /* 64 KB */
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#define EXYNOS4210_IRAM_BASE_ADDR 0x02020000
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#define EXYNOS4210_IRAM_SIZE 0x00020000 /* 128 KB */
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/* Secondary CPU startup code is in IROM memory */
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#define EXYNOS4210_SMP_BOOT_ADDR EXYNOS4210_IROM_BASE_ADDR
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#define EXYNOS4210_SMP_BOOT_SIZE 0x1000
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#define EXYNOS4210_BASE_BOOT_ADDR EXYNOS4210_DRAM0_BASE_ADDR
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/* Secondary CPU polling address to get loader start from */
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#define EXYNOS4210_SECOND_CPU_BOOTREG 0x10020814
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#define EXYNOS4210_SMP_PRIVATE_BASE_ADDR 0x10500000
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#define EXYNOS4210_L2X0_BASE_ADDR 0x10502000
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/*
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* exynos4210 IRQ subsystem stub definitions.
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*/
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@ -60,6 +82,24 @@ typedef struct Exynos4210Irq {
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qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
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} Exynos4210Irq;
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typedef struct Exynos4210State {
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CPUState * env[EXYNOS4210_NCPUS];
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Exynos4210Irq irqs;
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qemu_irq *irq_table;
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MemoryRegion chipid_mem;
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MemoryRegion iram_mem;
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MemoryRegion irom_mem;
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MemoryRegion irom_alias_mem;
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MemoryRegion dram0_mem;
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MemoryRegion dram1_mem;
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MemoryRegion boot_secondary;
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MemoryRegion bootreg_mem;
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} Exynos4210State;
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Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
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unsigned long ram_size);
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/* Initialize exynos4210 IRQ subsystem stub */
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qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
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153
hw/exynos4_boards.c
Normal file
153
hw/exynos4_boards.c
Normal file
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@ -0,0 +1,153 @@
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/*
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* Samsung exynos4 SoC based boards emulation
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
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* Maksim Kozlov <m.kozlov@samsung.com>
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* Evgeny Voevodin <e.voevodin@samsung.com>
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* Igor Mitsyanko <i.mitsyanko@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
|
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include "sysemu.h"
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#include "sysbus.h"
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#include "arm-misc.h"
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#include "exec-memory.h"
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#include "exynos4210.h"
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#include "boards.h"
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#undef DEBUG
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//#define DEBUG
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#ifdef DEBUG
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#undef PRINT_DEBUG
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#define PRINT_DEBUG(fmt, args...) \
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do { \
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fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
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} while (0)
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#else
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#define PRINT_DEBUG(fmt, args...) do {} while (0)
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#endif
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typedef enum Exynos4BoardType {
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EXYNOS4_BOARD_NURI,
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EXYNOS4_BOARD_SMDKC210,
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EXYNOS4_NUM_OF_BOARDS
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} Exynos4BoardType;
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static int exynos4_board_id[EXYNOS4_NUM_OF_BOARDS] = {
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[EXYNOS4_BOARD_NURI] = 0xD33,
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[EXYNOS4_BOARD_SMDKC210] = 0xB16,
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};
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static int exynos4_board_smp_bootreg_addr[EXYNOS4_NUM_OF_BOARDS] = {
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[EXYNOS4_BOARD_NURI] = EXYNOS4210_SECOND_CPU_BOOTREG,
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[EXYNOS4_BOARD_SMDKC210] = EXYNOS4210_SECOND_CPU_BOOTREG,
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};
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static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = {
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[EXYNOS4_BOARD_NURI] = 0x40000000,
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[EXYNOS4_BOARD_SMDKC210] = 0x40000000,
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};
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static struct arm_boot_info exynos4_board_binfo = {
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.loader_start = EXYNOS4210_BASE_BOOT_ADDR,
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.smp_loader_start = EXYNOS4210_SMP_BOOT_ADDR,
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.nb_cpus = EXYNOS4210_NCPUS,
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};
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static QEMUMachine exynos4_machines[EXYNOS4_NUM_OF_BOARDS];
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static Exynos4210State *exynos4_boards_init_common(
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const char *kernel_filename,
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const char *kernel_cmdline,
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const char *initrd_filename,
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Exynos4BoardType board_type)
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{
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if (smp_cpus != EXYNOS4210_NCPUS) {
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fprintf(stderr, "%s board supports only %d CPU cores. Ignoring smp_cpus"
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" value.\n",
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exynos4_machines[board_type].name,
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exynos4_machines[board_type].max_cpus);
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}
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exynos4_board_binfo.ram_size = exynos4_board_ram_size[board_type];
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exynos4_board_binfo.board_id = exynos4_board_id[board_type];
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exynos4_board_binfo.smp_bootreg_addr =
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exynos4_board_smp_bootreg_addr[board_type];
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exynos4_board_binfo.kernel_filename = kernel_filename;
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exynos4_board_binfo.initrd_filename = initrd_filename;
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exynos4_board_binfo.kernel_cmdline = kernel_cmdline;
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exynos4_board_binfo.smp_priv_base = EXYNOS4210_SMP_PRIVATE_BASE_ADDR;
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PRINT_DEBUG("\n ram_size: %luMiB [0x%08lx]\n"
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" kernel_filename: %s\n"
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" kernel_cmdline: %s\n"
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" initrd_filename: %s\n",
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exynos4_board_ram_size[board_type] / 1048576,
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exynos4_board_ram_size[board_type],
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kernel_filename,
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kernel_cmdline,
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initrd_filename);
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return exynos4210_init(get_system_memory(),
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exynos4_board_ram_size[board_type]);
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}
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static void nuri_init(ram_addr_t ram_size,
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const char *boot_device,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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exynos4_boards_init_common(kernel_filename, kernel_cmdline,
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initrd_filename, EXYNOS4_BOARD_NURI);
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arm_load_kernel(first_cpu, &exynos4_board_binfo);
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}
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static void smdkc210_init(ram_addr_t ram_size,
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const char *boot_device,
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const char *kernel_filename, const char *kernel_cmdline,
|
||||
const char *initrd_filename, const char *cpu_model)
|
||||
{
|
||||
exynos4_boards_init_common(kernel_filename, kernel_cmdline,
|
||||
initrd_filename, EXYNOS4_BOARD_SMDKC210);
|
||||
|
||||
arm_load_kernel(first_cpu, &exynos4_board_binfo);
|
||||
}
|
||||
|
||||
static QEMUMachine exynos4_machines[EXYNOS4_NUM_OF_BOARDS] = {
|
||||
[EXYNOS4_BOARD_NURI] = {
|
||||
.name = "nuri",
|
||||
.desc = "Samsung NURI board (Exynos4210)",
|
||||
.init = nuri_init,
|
||||
.max_cpus = EXYNOS4210_NCPUS,
|
||||
},
|
||||
[EXYNOS4_BOARD_SMDKC210] = {
|
||||
.name = "smdkc210",
|
||||
.desc = "Samsung SMDKC210 board (Exynos4210)",
|
||||
.init = smdkc210_init,
|
||||
.max_cpus = EXYNOS4210_NCPUS,
|
||||
},
|
||||
};
|
||||
|
||||
static void exynos4_machine_init(void)
|
||||
{
|
||||
qemu_register_machine(&exynos4_machines[EXYNOS4_BOARD_NURI]);
|
||||
qemu_register_machine(&exynos4_machines[EXYNOS4_BOARD_SMDKC210]);
|
||||
}
|
||||
|
||||
machine_init(exynos4_machine_init);
|
||||
Loading…
Reference in a new issue