haraldwolff/qemu-patch-raspberry4
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target/riscv: Alloc tcg global for cur_pm[mask|base]

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Replace the array of pm_mask/pm_base with scalar variables.
Remove the cached array value in DisasContext.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-13-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
LIU Zhiwei 2022-01-20 20:20:39 +08:00 committed by Alistair Francis
parent 40bfa5f695
commit 0cff460de9
1 changed files with 8 additions and 24 deletions
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32
target/riscv/translate.c
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@ -38,8 +38,8 @@ static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv load_res; static TCGv load_res;
static TCGv load_val; static TCGv load_val;
/* globals for PM CSRs */ /* globals for PM CSRs */
static TCGv pm_mask[4]; static TCGv pm_mask;
static TCGv pm_base[4]; static TCGv pm_base;
#include "exec/gen-icount.h" #include "exec/gen-icount.h"
@ -109,8 +109,6 @@ typedef struct DisasContext {
TCGv temp[4]; TCGv temp[4];
/* PointerMasking extension */ /* PointerMasking extension */
bool pm_enabled; bool pm_enabled;
TCGv pm_mask;
TCGv pm_base;
} DisasContext; } DisasContext;
static inline bool has_ext(DisasContext *ctx, uint32_t ext) static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@ -403,8 +401,8 @@ static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
return src; return src;
} else { } else {
temp = temp_new(s); temp = temp_new(s);
tcg_gen_andc_tl(temp, src, s->pm_mask); tcg_gen_andc_tl(temp, src, pm_mask);
tcg_gen_or_tl(temp, temp, s->pm_base); tcg_gen_or_tl(temp, temp, pm_base);
return temp; return temp;
} }
} }
@ -929,10 +927,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->ntemp = 0; ctx->ntemp = 0;
memset(ctx->temp, 0, sizeof(ctx->temp)); memset(ctx->temp, 0, sizeof(ctx->temp));
ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
int priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK;
ctx->pm_mask = pm_mask[priv];
ctx->pm_base = pm_base[priv];
ctx->zero = tcg_constant_tl(0); ctx->zero = tcg_constant_tl(0);
} }
@ -1050,19 +1044,9 @@ void riscv_translate_init(void)
"load_res"); "load_res");
load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
"load_val"); "load_val");
#ifndef CONFIG_USER_ONLY
/* Assign PM CSRs to tcg globals */ /* Assign PM CSRs to tcg globals */
pm_mask[PRV_U] = pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask),
tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask"); "pmmask");
pm_base[PRV_U] = pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase),
tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase"); "pmbase");
pm_mask[PRV_S] =
tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask");
pm_base[PRV_S] =
tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase");
pm_mask[PRV_M] =
tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask");
pm_base[PRV_M] =
tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase");
#endif
} }