hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit
v8.1M introduces a new TRD flag in the CCR register, which enables checking for stack frame integrity signatures on SG instructions. This bit is not banked, and is always RAZ/WI to Non-secure code. Adjust the code for handling CCR reads and writes to handle this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-23-peter.maydell@linaro.org
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@ -1095,8 +1095,9 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
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}
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}
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return cpu->env.v7m.scr[attrs.secure];
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return cpu->env.v7m.scr[attrs.secure];
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case 0xd14: /* Configuration Control. */
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case 0xd14: /* Configuration Control. */
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/* The BFHFNMIGN bit is the only non-banked bit; we
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/*
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* keep it in the non-secure copy of the register.
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* Non-banked bits: BFHFNMIGN (stored in the NS copy of the register)
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* and TRD (stored in the S copy of the register)
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*/
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*/
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val = cpu->env.v7m.ccr[attrs.secure];
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val = cpu->env.v7m.ccr[attrs.secure];
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val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;
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val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;
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@ -1639,17 +1640,25 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
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cpu->env.v7m.scr[attrs.secure] = value;
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cpu->env.v7m.scr[attrs.secure] = value;
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break;
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break;
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case 0xd14: /* Configuration Control. */
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case 0xd14: /* Configuration Control. */
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{
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uint32_t mask;
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if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
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if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
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goto bad_offset;
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goto bad_offset;
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}
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}
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/* Enforce RAZ/WI on reserved and must-RAZ/WI bits */
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/* Enforce RAZ/WI on reserved and must-RAZ/WI bits */
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value &= (R_V7M_CCR_STKALIGN_MASK |
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mask = R_V7M_CCR_STKALIGN_MASK |
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R_V7M_CCR_BFHFNMIGN_MASK |
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R_V7M_CCR_BFHFNMIGN_MASK |
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R_V7M_CCR_DIV_0_TRP_MASK |
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R_V7M_CCR_DIV_0_TRP_MASK |
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R_V7M_CCR_UNALIGN_TRP_MASK |
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R_V7M_CCR_UNALIGN_TRP_MASK |
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R_V7M_CCR_USERSETMPEND_MASK |
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R_V7M_CCR_USERSETMPEND_MASK |
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R_V7M_CCR_NONBASETHRDENA_MASK);
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R_V7M_CCR_NONBASETHRDENA_MASK;
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if (arm_feature(&cpu->env, ARM_FEATURE_V8_1M) && attrs.secure) {
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/* TRD is always RAZ/WI from NS */
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mask |= R_V7M_CCR_TRD_MASK;
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}
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value &= mask;
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if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
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if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
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/* v8M makes NONBASETHRDENA and STKALIGN be RES1 */
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/* v8M makes NONBASETHRDENA and STKALIGN be RES1 */
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@ -1666,6 +1675,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
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cpu->env.v7m.ccr[attrs.secure] = value;
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cpu->env.v7m.ccr[attrs.secure] = value;
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break;
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break;
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}
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case 0xd24: /* System Handler Control and State (SHCSR) */
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case 0xd24: /* System Handler Control and State (SHCSR) */
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if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) {
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if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) {
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goto bad_offset;
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goto bad_offset;
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@ -1611,6 +1611,8 @@ FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
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FIELD(V7M_CCR, DC, 16, 1)
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FIELD(V7M_CCR, DC, 16, 1)
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FIELD(V7M_CCR, IC, 17, 1)
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FIELD(V7M_CCR, IC, 17, 1)
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FIELD(V7M_CCR, BP, 18, 1)
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FIELD(V7M_CCR, BP, 18, 1)
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FIELD(V7M_CCR, LOB, 19, 1)
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FIELD(V7M_CCR, TRD, 20, 1)
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/* V7M SCR bits */
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/* V7M SCR bits */
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FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
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FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
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