stm32f100: Add the stm32f100 SoC
This SoC is similar to stm32f205 SoC. This will be used by the STM32VLDISCOVERY to create a machine. Signed-off-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210617165647.2575955-2-erdnaxe@crans.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>stable-6.1
Alexandre Iooss
Peter Maydell
parent
05de778b5b
commit
0f76debd1f
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@ -948,6 +948,12 @@ L: qemu-arm@nongnu.org
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S: Maintained
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F: hw/arm/virt-acpi-build.c
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STM32F100
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M: Alexandre Iooss <erdnaxe@crans.org>
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L: qemu-arm@nongnu.org
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S: Maintained
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F: hw/arm/stm32f100_soc.c
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STM32F205
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M: Alistair Francis <alistair@alistair23.me>
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M: Peter Maydell <peter.maydell@linaro.org>
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@ -326,6 +326,12 @@ config RASPI
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select SDHCI
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select USB_DWC2
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config STM32F100_SOC
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bool
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select ARM_V7M
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select STM32F2XX_USART
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select STM32F2XX_SPI
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config STM32F205_SOC
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bool
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select ARM_V7M
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@ -39,6 +39,7 @@ arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c'))
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arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c'))
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arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c'))
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arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c', 'bcm2836.c', 'raspi.c'))
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arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c'))
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arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c'))
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arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c'))
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arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c'))
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@ -0,0 +1,182 @@
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/*
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* STM32F100 SoC
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*
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* Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
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* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "hw/arm/boot.h"
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#include "exec/address-spaces.h"
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#include "hw/arm/stm32f100_soc.h"
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#include "hw/qdev-properties.h"
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#include "hw/misc/unimp.h"
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#include "sysemu/sysemu.h"
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/* stm32f100_soc implementation is derived from stm32f205_soc */
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static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40013800, 0x40004400,
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0x40004800 };
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static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800 };
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static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39};
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static const int spi_irq[STM_NUM_SPIS] = {35, 36};
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static void stm32f100_soc_initfn(Object *obj)
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{
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STM32F100State *s = STM32F100_SOC(obj);
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int i;
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object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
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for (i = 0; i < STM_NUM_USARTS; i++) {
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object_initialize_child(obj, "usart[*]", &s->usart[i],
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TYPE_STM32F2XX_USART);
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}
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for (i = 0; i < STM_NUM_SPIS; i++) {
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object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
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}
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}
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static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
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{
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STM32F100State *s = STM32F100_SOC(dev_soc);
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DeviceState *dev, *armv7m;
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SysBusDevice *busdev;
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int i;
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *sram = g_new(MemoryRegion, 1);
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MemoryRegion *flash = g_new(MemoryRegion, 1);
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MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
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/*
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* Init flash region
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* Flash starts at 0x08000000 and then is aliased to boot memory at 0x0
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*/
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memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F100.flash",
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FLASH_SIZE, &error_fatal);
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memory_region_init_alias(flash_alias, OBJECT(dev_soc),
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"STM32F100.flash.alias", flash, 0, FLASH_SIZE);
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memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
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memory_region_add_subregion(system_memory, 0, flash_alias);
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/* Init SRAM region */
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memory_region_init_ram(sram, NULL, "STM32F100.sram", SRAM_SIZE,
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&error_fatal);
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memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
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/* Init ARMv7m */
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armv7m = DEVICE(&s->armv7m);
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qdev_prop_set_uint32(armv7m, "num-irq", 61);
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qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
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qdev_prop_set_bit(armv7m, "enable-bitband", true);
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object_property_set_link(OBJECT(&s->armv7m), "memory",
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OBJECT(get_system_memory()), &error_abort);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
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return;
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}
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/* Attach UART (uses USART registers) and USART controllers */
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for (i = 0; i < STM_NUM_USARTS; i++) {
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dev = DEVICE(&(s->usart[i]));
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qdev_prop_set_chr(dev, "chardev", serial_hd(i));
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) {
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return;
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}
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, usart_addr[i]);
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sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
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}
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/* SPI 1 and 2 */
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for (i = 0; i < STM_NUM_SPIS; i++) {
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dev = DEVICE(&(s->spi[i]));
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
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return;
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}
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, spi_addr[i]);
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sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
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}
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create_unimplemented_device("timer[2]", 0x40000000, 0x400);
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create_unimplemented_device("timer[3]", 0x40000400, 0x400);
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create_unimplemented_device("timer[4]", 0x40000800, 0x400);
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create_unimplemented_device("timer[6]", 0x40001000, 0x400);
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create_unimplemented_device("timer[7]", 0x40001400, 0x400);
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create_unimplemented_device("RTC", 0x40002800, 0x400);
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create_unimplemented_device("WWDG", 0x40002C00, 0x400);
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create_unimplemented_device("IWDG", 0x40003000, 0x400);
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create_unimplemented_device("I2C1", 0x40005400, 0x400);
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create_unimplemented_device("I2C2", 0x40005800, 0x400);
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create_unimplemented_device("BKP", 0x40006C00, 0x400);
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create_unimplemented_device("PWR", 0x40007000, 0x400);
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create_unimplemented_device("DAC", 0x40007400, 0x400);
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create_unimplemented_device("CEC", 0x40007800, 0x400);
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create_unimplemented_device("AFIO", 0x40010000, 0x400);
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create_unimplemented_device("EXTI", 0x40010400, 0x400);
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create_unimplemented_device("GPIOA", 0x40010800, 0x400);
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create_unimplemented_device("GPIOB", 0x40010C00, 0x400);
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create_unimplemented_device("GPIOC", 0x40011000, 0x400);
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create_unimplemented_device("GPIOD", 0x40011400, 0x400);
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create_unimplemented_device("GPIOE", 0x40011800, 0x400);
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create_unimplemented_device("ADC1", 0x40012400, 0x400);
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create_unimplemented_device("timer[1]", 0x40012C00, 0x400);
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create_unimplemented_device("timer[15]", 0x40014000, 0x400);
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create_unimplemented_device("timer[16]", 0x40014400, 0x400);
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create_unimplemented_device("timer[17]", 0x40014800, 0x400);
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create_unimplemented_device("DMA", 0x40020000, 0x400);
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create_unimplemented_device("RCC", 0x40021000, 0x400);
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create_unimplemented_device("Flash Int", 0x40022000, 0x400);
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create_unimplemented_device("CRC", 0x40023000, 0x400);
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}
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static Property stm32f100_soc_properties[] = {
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DEFINE_PROP_STRING("cpu-type", STM32F100State, cpu_type),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void stm32f100_soc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = stm32f100_soc_realize;
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device_class_set_props(dc, stm32f100_soc_properties);
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}
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static const TypeInfo stm32f100_soc_info = {
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.name = TYPE_STM32F100_SOC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(STM32F100State),
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.instance_init = stm32f100_soc_initfn,
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.class_init = stm32f100_soc_class_init,
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};
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static void stm32f100_soc_types(void)
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{
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type_register_static(&stm32f100_soc_info);
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}
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type_init(stm32f100_soc_types)
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@ -0,0 +1,57 @@
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/*
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* STM32F100 SoC
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*
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* Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef HW_ARM_STM32F100_SOC_H
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#define HW_ARM_STM32F100_SOC_H
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#include "hw/char/stm32f2xx_usart.h"
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#include "hw/ssi/stm32f2xx_spi.h"
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#include "hw/arm/armv7m.h"
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#include "qom/object.h"
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#define TYPE_STM32F100_SOC "stm32f100-soc"
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OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC)
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#define STM_NUM_USARTS 3
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#define STM_NUM_SPIS 2
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#define FLASH_BASE_ADDRESS 0x08000000
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#define FLASH_SIZE (128 * 1024)
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#define SRAM_BASE_ADDRESS 0x20000000
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#define SRAM_SIZE (8 * 1024)
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struct STM32F100State {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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char *cpu_type;
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ARMv7MState armv7m;
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STM32F2XXUsartState usart[STM_NUM_USARTS];
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STM32F2XXSPIState spi[STM_NUM_SPIS];
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};
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#endif
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