hw/arm/iotkit-sysctl: Implement CPUWAIT and INITSVTOR*
The CPUWAIT register acts as a sort of power-control: if a bit in it is 1 then the CPU will have been forced into waiting when the system was reset (which in QEMU we model as the CPU starting powered off). Writing a 0 to the register will allow the CPU to boot (for QEMU, we model this as powering it on). Note that writing 0 to the register does not power off a CPU. For this to work correctly we need to also honour the INITSVTOR* registers, which let the guest control where the CPU will load its SP and PC from when it comes out of reset. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190219125808.25174-8-peter.maydell@linaro.org
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@ -25,6 +25,8 @@
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#include "hw/sysbus.h"
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#include "hw/registerfields.h"
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#include "hw/misc/iotkit-sysctl.h"
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#include "target/arm/arm-powerctl.h"
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#include "target/arm/cpu.h"
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REG32(SECDBGSTAT, 0x0)
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REG32(SECDBGSET, 0x4)
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@ -69,6 +71,21 @@ static const int sysctl_id[] = {
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0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
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};
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/*
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* Set the initial secure vector table offset address for the core.
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* This will take effect when the CPU next resets.
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*/
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static void set_init_vtor(uint64_t cpuid, uint32_t vtor)
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{
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Object *cpuobj = OBJECT(arm_get_cpu_by_id(cpuid));
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if (cpuobj) {
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if (object_property_find(cpuobj, "init-svtor", NULL)) {
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object_property_set_uint(cpuobj, vtor, "init-svtor", &error_abort);
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}
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}
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}
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static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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@ -229,11 +246,18 @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
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s->gretreg = value;
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break;
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case A_INITSVTOR0:
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR0 unimplemented\n");
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s->initsvtor0 = value;
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set_init_vtor(0, s->initsvtor0);
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break;
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case A_CPUWAIT:
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CPUWAIT unimplemented\n");
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if ((s->cpuwait & 1) && !(value & 1)) {
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/* Powering up CPU 0 */
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arm_set_cpu_on_and_reset(0);
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}
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if ((s->cpuwait & 2) && !(value & 2)) {
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/* Powering up CPU 1 */
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arm_set_cpu_on_and_reset(1);
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}
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s->cpuwait = value;
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break;
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case A_WICCTRL:
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@ -287,8 +311,8 @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
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if (!s->is_sse200) {
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goto bad_offset;
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}
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR1 unimplemented\n");
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s->initsvtor1 = value;
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set_init_vtor(1, s->initsvtor1);
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break;
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case A_EWCTRL:
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if (!s->is_sse200) {
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@ -382,7 +406,16 @@ static void iotkit_sysctl_reset(DeviceState *dev)
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s->gretreg = 0;
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s->initsvtor0 = 0x10000000;
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s->initsvtor1 = 0x10000000;
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if (s->is_sse200) {
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/*
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* CPU 0 starts on, CPU 1 starts off. In real hardware this is
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* configurable by the SoC integrator as a verilog parameter.
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*/
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s->cpuwait = 2;
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} else {
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/* CPU 0 starts on */
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s->cpuwait = 0;
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}
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s->wicctrl = 0;
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s->scsecctrl = 0;
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s->fclk_div = 0;
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