I2C/SMBus framework.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2845 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
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c6fdf5fca0
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@ -402,6 +402,8 @@ SOUND_HW += fmopl.o adlib.o
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endif
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endif
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AUDIODRV+= wavcapture.o
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AUDIODRV+= wavcapture.o
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VL_OBJS += i2c.o smbus.o
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# SCSI layer
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# SCSI layer
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VL_OBJS+= scsi-disk.o cdrom.o lsi53c895a.o
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VL_OBJS+= scsi-disk.o cdrom.o lsi53c895a.o
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57
hw/acpi.c
57
hw/acpi.c
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@ -35,7 +35,7 @@ typedef struct PIIX4PMState {
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uint8_t apms;
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uint8_t apms;
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QEMUTimer *tmr_timer;
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QEMUTimer *tmr_timer;
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int64_t tmr_overflow_time;
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int64_t tmr_overflow_time;
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SMBusDevice *smb_dev[128];
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i2c_bus *smbus;
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uint8_t smb_stat;
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uint8_t smb_stat;
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uint8_t smb_ctl;
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uint8_t smb_ctl;
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uint8_t smb_cmd;
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uint8_t smb_cmd;
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@ -63,9 +63,6 @@ typedef struct PIIX4PMState {
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#define SMBHSTDAT1 0x06
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#define SMBHSTDAT1 0x06
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#define SMBBLKDAT 0x07
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#define SMBBLKDAT 0x07
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/* Note: only used for piix4_smbus_register_device */
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static PIIX4PMState *piix4_pm_state;
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static uint32_t get_pmtmr(PIIX4PMState *s)
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static uint32_t get_pmtmr(PIIX4PMState *s)
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{
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{
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uint32_t d;
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uint32_t d;
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@ -258,59 +255,44 @@ static void smb_transaction(PIIX4PMState *s)
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uint8_t read = s->smb_addr & 0x01;
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uint8_t read = s->smb_addr & 0x01;
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uint8_t cmd = s->smb_cmd;
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uint8_t cmd = s->smb_cmd;
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uint8_t addr = s->smb_addr >> 1;
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uint8_t addr = s->smb_addr >> 1;
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SMBusDevice *dev = s->smb_dev[addr];
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i2c_bus *bus = s->smbus;
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#ifdef DEBUG
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#ifdef DEBUG
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printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
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printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
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#endif
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#endif
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if (!dev) goto error;
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switch(prot) {
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switch(prot) {
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case 0x0:
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case 0x0:
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if (!dev->quick_cmd) goto error;
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smbus_quick_command(bus, addr, read);
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(*dev->quick_cmd)(dev, read);
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break;
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break;
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case 0x1:
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case 0x1:
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if (read) {
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if (read) {
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if (!dev->receive_byte) goto error;
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s->smb_data0 = smbus_receive_byte(bus, addr);
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s->smb_data0 = (*dev->receive_byte)(dev);
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} else {
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}
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smbus_send_byte(bus, addr, cmd);
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else {
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if (!dev->send_byte) goto error;
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(*dev->send_byte)(dev, cmd);
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}
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}
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break;
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break;
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case 0x2:
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case 0x2:
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if (read) {
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if (read) {
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if (!dev->read_byte) goto error;
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s->smb_data0 = smbus_read_byte(bus, addr, cmd);
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s->smb_data0 = (*dev->read_byte)(dev, cmd);
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} else {
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}
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smbus_write_byte(bus, addr, cmd, s->smb_data0);
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else {
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if (!dev->write_byte) goto error;
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(*dev->write_byte)(dev, cmd, s->smb_data0);
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}
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}
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break;
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break;
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case 0x3:
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case 0x3:
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if (read) {
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if (read) {
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uint16_t val;
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uint16_t val;
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if (!dev->read_word) goto error;
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val = smbus_read_word(bus, addr, cmd);
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val = (*dev->read_word)(dev, cmd);
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s->smb_data0 = val;
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s->smb_data0 = val;
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s->smb_data1 = val >> 8;
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s->smb_data1 = val >> 8;
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}
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} else {
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else {
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smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
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if (!dev->write_word) goto error;
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(*dev->write_word)(dev, cmd, (s->smb_data1 << 8) | s->smb_data0);
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}
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}
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break;
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break;
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case 0x5:
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case 0x5:
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if (read) {
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if (read) {
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if (!dev->read_block) goto error;
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s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
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s->smb_data0 = (*dev->read_block)(dev, cmd, s->smb_data);
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} else {
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}
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smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
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else {
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if (!dev->write_block) goto error;
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(*dev->write_block)(dev, cmd, s->smb_data0, s->smb_data);
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}
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}
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break;
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break;
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default:
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default:
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@ -469,7 +451,7 @@ static int pm_load(QEMUFile* f,void* opaque,int version_id)
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return 0;
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return 0;
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}
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}
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void piix4_pm_init(PCIBus *bus, int devfn)
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i2c_bus *piix4_pm_init(PCIBus *bus, int devfn)
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{
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{
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PIIX4PMState *s;
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PIIX4PMState *s;
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uint8_t *pci_conf;
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uint8_t *pci_conf;
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@ -514,10 +496,7 @@ void piix4_pm_init(PCIBus *bus, int devfn)
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s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
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s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
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register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);
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register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);
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piix4_pm_state = s;
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}
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void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr)
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s->smbus = i2c_init_bus();
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{
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return s->smbus;
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piix4_pm_state->smb_dev[addr] = dev;
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}
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}
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117
hw/i2c.c
Normal file
117
hw/i2c.c
Normal file
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@ -0,0 +1,117 @@
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/*
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* QEMU I2C bus interface.
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*
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* Copyright (c) 2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licenced under the LGPL.
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*/
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#include "vl.h"
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struct i2c_bus
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{
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i2c_slave *current_dev;
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i2c_slave *dev;
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};
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/* Create a new I2C bus. */
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i2c_bus *i2c_init_bus(void)
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{
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i2c_bus *bus;
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bus = (i2c_bus *)qemu_mallocz(sizeof(i2c_bus));
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return bus;
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}
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/* Create a new slave device. */
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i2c_slave *i2c_slave_init(i2c_bus *bus, int address, int size)
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{
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i2c_slave *dev;
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if (size < sizeof(i2c_slave))
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cpu_abort(cpu_single_env, "I2C struct too small");
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dev = (i2c_slave *)qemu_mallocz(size);
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dev->address = address;
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dev->next = bus->dev;
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bus->dev = dev;
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return dev;
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}
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void i2c_set_slave_address(i2c_slave *dev, int address)
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{
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dev->address = address;
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}
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/* Return nonzero if bus is busy. */
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int i2c_bus_busy(i2c_bus *bus)
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{
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return bus->current_dev != NULL;
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}
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/* Returns nonzero if the bus is already busy, or is the address is not
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valid. */
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/* TODO: Make this handle multiple masters. */
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int i2c_start_transfer(i2c_bus *bus, int address, int recv)
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{
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i2c_slave *dev;
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for (dev = bus->dev; dev; dev = dev->next) {
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if (dev->address == address)
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break;
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}
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if (!dev)
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return 1;
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/* If the bus is already busy, assume this is a repeated
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start condition. */
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bus->current_dev = dev;
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dev->event(dev, recv ? I2C_START_RECV : I2C_START_SEND);
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return 0;
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}
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void i2c_end_transfer(i2c_bus *bus)
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{
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i2c_slave *dev = bus->current_dev;
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if (!dev)
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return;
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dev->event(dev, I2C_FINISH);
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bus->current_dev = NULL;
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}
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int i2c_send(i2c_bus *bus, uint8_t data)
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{
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i2c_slave *dev = bus->current_dev;
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if (!dev)
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return -1;
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return dev->send(dev, data);
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}
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int i2c_recv(i2c_bus *bus)
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{
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i2c_slave *dev = bus->current_dev;
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if (!dev)
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return -1;
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return dev->recv(dev);
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}
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void i2c_nack(i2c_bus *bus)
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{
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i2c_slave *dev = bus->current_dev;
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if (!dev)
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return;
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dev->event(dev, I2C_NACK);
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}
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49
hw/i2c.h
Normal file
49
hw/i2c.h
Normal file
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@ -0,0 +1,49 @@
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#ifndef QEMU_I2C_H
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#define QEMU_I2C_H
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/* The QEMU I2C implementation only supports simple transfers that complete
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immediately. It does not support slave devices that need to be able to
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defer their response (eg. CPU slave interfaces where the data is supplied
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by the device driver in response to an interrupt). */
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enum i2c_event {
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I2C_START_RECV,
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I2C_START_SEND,
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I2C_FINISH,
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I2C_NACK /* Masker NACKed a recieve byte. */
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};
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typedef struct i2c_slave i2c_slave;
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/* Master to slave. */
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typedef int (*i2c_send_cb)(i2c_slave *s, uint8_t data);
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/* Slave to master. */
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typedef int (*i2c_recv_cb)(i2c_slave *s);
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/* Notify the slave of a bus state change. */
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typedef void (*i2c_event_cb)(i2c_slave *s, enum i2c_event event);
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struct i2c_slave
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{
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/* Callbacks to be set by the device. */
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i2c_event_cb event;
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i2c_recv_cb recv;
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i2c_send_cb send;
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/* Remaining fields for internal use by the I2C code. */
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int address;
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void *next;
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};
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typedef struct i2c_bus i2c_bus;
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i2c_bus *i2c_init_bus(void);
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i2c_slave *i2c_slave_init(i2c_bus *bus, int address, int size);
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void i2c_set_slave_address(i2c_slave *dev, int address);
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int i2c_bus_busy(i2c_bus *bus);
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int i2c_start_transfer(i2c_bus *bus, int address, int recv);
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void i2c_end_transfer(i2c_bus *bus);
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void i2c_nack(i2c_bus *bus);
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int i2c_send(i2c_bus *bus, uint8_t data);
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int i2c_recv(i2c_bus *bus);
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#endif
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9
hw/pc.c
9
hw/pc.c
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@ -897,11 +897,12 @@ static void pc_init1(int ram_size, int vga_ram_size, int boot_device,
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if (pci_enabled && acpi_enabled) {
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if (pci_enabled && acpi_enabled) {
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uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
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uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
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piix4_pm_init(pci_bus, piix3_devfn + 3);
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i2c_bus *smbus;
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/* TODO: Populate SPD eeprom data. */
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smbus = piix4_pm_init(pci_bus, piix3_devfn + 3);
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for (i = 0; i < 8; i++) {
|
for (i = 0; i < 8; i++) {
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SMBusDevice *eeprom = smbus_eeprom_device_init(0x50 + i,
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smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256));
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eeprom_buf + (i * 256));
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piix4_smbus_register_device(eeprom, 0x50 + i);
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}
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}
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}
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}
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|
303
hw/smbus.c
Normal file
303
hw/smbus.c
Normal file
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@ -0,0 +1,303 @@
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/*
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* QEMU SMBus device emulation.
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*
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* Copyright (c) 2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licenced under the LGPL.
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|
*/
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/* TODO: Implement PEC. */
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|
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#include "vl.h"
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//#define DEBUG_SMBUS 1
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|
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|
#ifdef DEBUG_SMBUS
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#define DPRINTF(fmt, args...) \
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do { printf("smbus(%02x): " fmt , dev->i2c.address, ##args); } while (0)
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|
#define BADF(fmt, args...) \
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do { fprintf(stderr, "smbus: error: " fmt , ##args); exit(1);} while (0)
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#else
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#define DPRINTF(fmt, args...) do {} while(0)
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#define BADF(fmt, args...) \
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do { fprintf(stderr, "smbus: error: " fmt , ##args);} while (0)
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#endif
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|
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|
enum {
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|
SMBUS_IDLE,
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|
SMBUS_WRITE_DATA,
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|
SMBUS_RECV_BYTE,
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|
SMBUS_READ_DATA,
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|
SMBUS_DONE,
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|
SMBUS_CONFUSED = -1
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|
};
|
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|
|
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|
static void smbus_do_quick_cmd(SMBusDevice *dev, int recv)
|
||||||
|
{
|
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|
DPRINTF("Quick Command %d\n", recv);
|
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|
if (dev->quick_cmd)
|
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|
dev->quick_cmd(dev, recv);
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|
}
|
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|
|
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|
static void smbus_do_write(SMBusDevice *dev)
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||||||
|
{
|
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|
if (dev->data_len == 0) {
|
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|
smbus_do_quick_cmd(dev, 0);
|
||||||
|
} else if (dev->data_len == 1) {
|
||||||
|
DPRINTF("Send Byte\n");
|
||||||
|
if (dev->send_byte) {
|
||||||
|
dev->send_byte(dev, dev->data_buf[0]);
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
dev->command = dev->data_buf[0];
|
||||||
|
DPRINTF("Command %d len %d\n", dev->command, dev->data_len - 1);
|
||||||
|
if (dev->write_data) {
|
||||||
|
dev->write_data(dev, dev->command, dev->data_buf + 1,
|
||||||
|
dev->data_len - 1);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void smbus_i2c_event(i2c_slave *s, enum i2c_event event)
|
||||||
|
{
|
||||||
|
SMBusDevice *dev = (SMBusDevice *)s;
|
||||||
|
switch (event) {
|
||||||
|
case I2C_START_SEND:
|
||||||
|
switch (dev->mode) {
|
||||||
|
case SMBUS_IDLE:
|
||||||
|
DPRINTF("Incoming data\n");
|
||||||
|
dev->mode = SMBUS_WRITE_DATA;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
BADF("Unexpected send start condition in state %d\n", dev->mode);
|
||||||
|
dev->mode = SMBUS_CONFUSED;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case I2C_START_RECV:
|
||||||
|
switch (dev->mode) {
|
||||||
|
case SMBUS_IDLE:
|
||||||
|
DPRINTF("Read mode\n");
|
||||||
|
dev->mode = SMBUS_RECV_BYTE;
|
||||||
|
break;
|
||||||
|
case SMBUS_WRITE_DATA:
|
||||||
|
if (dev->data_len == 0) {
|
||||||
|
BADF("Read after write with no data\n");
|
||||||
|
dev->mode = SMBUS_CONFUSED;
|
||||||
|
} else {
|
||||||
|
if (dev->data_len > 1) {
|
||||||
|
smbus_do_write(dev);
|
||||||
|
} else {
|
||||||
|
dev->command = dev->data_buf[0];
|
||||||
|
DPRINTF("%02x: Command %d\n", dev->i2c.address,
|
||||||
|
dev->command);
|
||||||
|
}
|
||||||
|
DPRINTF("Read mode\n");
|
||||||
|
dev->data_len = 0;
|
||||||
|
dev->mode = SMBUS_READ_DATA;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
BADF("Unexpected recv start condition in state %d\n", dev->mode);
|
||||||
|
dev->mode = SMBUS_CONFUSED;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case I2C_FINISH:
|
||||||
|
switch (dev->mode) {
|
||||||
|
case SMBUS_WRITE_DATA:
|
||||||
|
smbus_do_write(dev);
|
||||||
|
break;
|
||||||
|
case SMBUS_RECV_BYTE:
|
||||||
|
smbus_do_quick_cmd(dev, 1);
|
||||||
|
break;
|
||||||
|
case SMBUS_READ_DATA:
|
||||||
|
BADF("Unexpected stop during receive\n");
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
/* Nothing to do. */
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
dev->mode = SMBUS_IDLE;
|
||||||
|
dev->data_len = 0;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case I2C_NACK:
|
||||||
|
switch (dev->mode) {
|
||||||
|
case SMBUS_DONE:
|
||||||
|
/* Nothing to do. */
|
||||||
|
break;
|
||||||
|
case SMBUS_READ_DATA:
|
||||||
|
dev->mode = SMBUS_DONE;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
BADF("Unexpected NACK in state %d\n", dev->mode);
|
||||||
|
dev->mode = SMBUS_CONFUSED;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static int smbus_i2c_recv(i2c_slave *s)
|
||||||
|
{
|
||||||
|
SMBusDevice *dev = (SMBusDevice *)s;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
switch (dev->mode) {
|
||||||
|
case SMBUS_RECV_BYTE:
|
||||||
|
if (dev->receive_byte) {
|
||||||
|
ret = dev->receive_byte(dev);
|
||||||
|
} else {
|
||||||
|
ret = 0;
|
||||||
|
}
|
||||||
|
DPRINTF("Receive Byte %02x\n", ret);
|
||||||
|
dev->mode = SMBUS_DONE;
|
||||||
|
break;
|
||||||
|
case SMBUS_READ_DATA:
|
||||||
|
if (dev->read_data) {
|
||||||
|
ret = dev->read_data(dev, dev->command, dev->data_len);
|
||||||
|
dev->data_len++;
|
||||||
|
} else {
|
||||||
|
ret = 0;
|
||||||
|
}
|
||||||
|
DPRINTF("Read data %02x\n", ret);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
BADF("Unexpected read in state %d\n", dev->mode);
|
||||||
|
dev->mode = SMBUS_CONFUSED;
|
||||||
|
ret = 0;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int smbus_i2c_send(i2c_slave *s, uint8_t data)
|
||||||
|
{
|
||||||
|
SMBusDevice *dev = (SMBusDevice *)s;
|
||||||
|
switch (dev->mode) {
|
||||||
|
case SMBUS_WRITE_DATA:
|
||||||
|
DPRINTF("Write data %02x\n", data);
|
||||||
|
dev->data_buf[dev->data_len++] = data;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
BADF("Unexpected write in state %d\n", dev->mode);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
SMBusDevice *smbus_device_init(i2c_bus *bus, int address, int size)
|
||||||
|
{
|
||||||
|
SMBusDevice *dev;
|
||||||
|
|
||||||
|
dev = (SMBusDevice *)i2c_slave_init(bus, address, size);
|
||||||
|
dev->i2c.event = smbus_i2c_event;
|
||||||
|
dev->i2c.recv = smbus_i2c_recv;
|
||||||
|
dev->i2c.send = smbus_i2c_send;
|
||||||
|
|
||||||
|
return dev;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Master device commands. */
|
||||||
|
void smbus_quick_command(i2c_bus *bus, int addr, int read)
|
||||||
|
{
|
||||||
|
i2c_start_transfer(bus, addr, read);
|
||||||
|
i2c_end_transfer(bus);
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8_t smbus_receive_byte(i2c_bus *bus, int addr)
|
||||||
|
{
|
||||||
|
uint8_t data;
|
||||||
|
|
||||||
|
i2c_start_transfer(bus, addr, 1);
|
||||||
|
data = i2c_recv(bus);
|
||||||
|
i2c_nack(bus);
|
||||||
|
i2c_end_transfer(bus);
|
||||||
|
return data;
|
||||||
|
}
|
||||||
|
|
||||||
|
void smbus_send_byte(i2c_bus *bus, int addr, uint8_t data)
|
||||||
|
{
|
||||||
|
i2c_start_transfer(bus, addr, 0);
|
||||||
|
i2c_send(bus, data);
|
||||||
|
i2c_end_transfer(bus);
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8_t smbus_read_byte(i2c_bus *bus, int addr, uint8_t command)
|
||||||
|
{
|
||||||
|
uint8_t data;
|
||||||
|
i2c_start_transfer(bus, addr, 0);
|
||||||
|
i2c_send(bus, command);
|
||||||
|
i2c_start_transfer(bus, addr, 1);
|
||||||
|
data = i2c_recv(bus);
|
||||||
|
i2c_nack(bus);
|
||||||
|
i2c_end_transfer(bus);
|
||||||
|
return data;
|
||||||
|
}
|
||||||
|
|
||||||
|
void smbus_write_byte(i2c_bus *bus, int addr, uint8_t command, uint8_t data)
|
||||||
|
{
|
||||||
|
i2c_start_transfer(bus, addr, 0);
|
||||||
|
i2c_send(bus, command);
|
||||||
|
i2c_send(bus, data);
|
||||||
|
i2c_end_transfer(bus);
|
||||||
|
}
|
||||||
|
|
||||||
|
uint16_t smbus_read_word(i2c_bus *bus, int addr, uint8_t command)
|
||||||
|
{
|
||||||
|
uint16_t data;
|
||||||
|
i2c_start_transfer(bus, addr, 0);
|
||||||
|
i2c_send(bus, command);
|
||||||
|
i2c_start_transfer(bus, addr, 1);
|
||||||
|
data = i2c_recv(bus);
|
||||||
|
data |= i2c_recv(bus) << 8;
|
||||||
|
i2c_nack(bus);
|
||||||
|
i2c_end_transfer(bus);
|
||||||
|
return data;
|
||||||
|
}
|
||||||
|
|
||||||
|
void smbus_write_word(i2c_bus *bus, int addr, uint8_t command, uint16_t data)
|
||||||
|
{
|
||||||
|
i2c_start_transfer(bus, addr, 0);
|
||||||
|
i2c_send(bus, command);
|
||||||
|
i2c_send(bus, data & 0xff);
|
||||||
|
i2c_send(bus, data >> 8);
|
||||||
|
i2c_end_transfer(bus);
|
||||||
|
}
|
||||||
|
|
||||||
|
int smbus_read_block(i2c_bus *bus, int addr, uint8_t command, uint8_t *data)
|
||||||
|
{
|
||||||
|
int len;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
i2c_start_transfer(bus, addr, 0);
|
||||||
|
i2c_send(bus, command);
|
||||||
|
i2c_start_transfer(bus, addr, 1);
|
||||||
|
len = i2c_recv(bus);
|
||||||
|
if (len > 32)
|
||||||
|
len = 0;
|
||||||
|
for (i = 0; i < len; i++)
|
||||||
|
data[i] = i2c_recv(bus);
|
||||||
|
i2c_nack(bus);
|
||||||
|
i2c_end_transfer(bus);
|
||||||
|
return len;
|
||||||
|
}
|
||||||
|
|
||||||
|
void smbus_write_block(i2c_bus *bus, int addr, uint8_t command, uint8_t *data,
|
||||||
|
int len)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
if (len > 32)
|
||||||
|
len = 32;
|
||||||
|
|
||||||
|
i2c_start_transfer(bus, addr, 0);
|
||||||
|
i2c_send(bus, command);
|
||||||
|
i2c_send(bus, len);
|
||||||
|
for (i = 0; i < len; i++)
|
||||||
|
i2c_send(bus, data[i]);
|
||||||
|
i2c_end_transfer(bus);
|
||||||
|
}
|
46
hw/smbus.h
46
hw/smbus.h
|
@ -25,14 +25,46 @@
|
||||||
typedef struct SMBusDevice SMBusDevice;
|
typedef struct SMBusDevice SMBusDevice;
|
||||||
|
|
||||||
struct SMBusDevice {
|
struct SMBusDevice {
|
||||||
uint8_t addr;
|
/* The SMBus protocol is implemented on top of I2C. */
|
||||||
|
i2c_slave i2c;
|
||||||
|
|
||||||
|
/* Callbacks set by the device. */
|
||||||
void (*quick_cmd)(SMBusDevice *dev, uint8_t read);
|
void (*quick_cmd)(SMBusDevice *dev, uint8_t read);
|
||||||
void (*send_byte)(SMBusDevice *dev, uint8_t val);
|
void (*send_byte)(SMBusDevice *dev, uint8_t val);
|
||||||
uint8_t (*receive_byte)(SMBusDevice *dev);
|
uint8_t (*receive_byte)(SMBusDevice *dev);
|
||||||
void (*write_byte)(SMBusDevice *dev, uint8_t cmd, uint8_t val);
|
/* We can't distinguish between a word write and a block write with
|
||||||
uint8_t (*read_byte)(SMBusDevice *dev, uint8_t cmd);
|
length 1, so pass the whole data block including the length byte
|
||||||
void (*write_word)(SMBusDevice *dev, uint8_t cmd, uint16_t val);
|
(if present). The device is responsible figuring out what type of
|
||||||
uint16_t (*read_word)(SMBusDevice *dev, uint8_t cmd);
|
command this is. */
|
||||||
void (*write_block)(SMBusDevice *dev, uint8_t cmd, uint8_t len, uint8_t *buf);
|
void (*write_data)(SMBusDevice *dev, uint8_t cmd, uint8_t *buf, int len);
|
||||||
uint8_t (*read_block)(SMBusDevice *dev, uint8_t cmd, uint8_t *buf);
|
/* Likewise we can't distinguish between defferent reads, or even know
|
||||||
|
the length of the read until the read is complete, so read data a
|
||||||
|
byte at a time. The device is responsible for adding the length
|
||||||
|
byte on block reads. */
|
||||||
|
uint8_t (*read_data)(SMBusDevice *dev, uint8_t cmd, int n);
|
||||||
|
|
||||||
|
/* Remaining fields for internal use only. */
|
||||||
|
int mode;
|
||||||
|
int data_len;
|
||||||
|
uint8_t data_buf[34]; /* command + len + 32 bytes of data. */
|
||||||
|
uint8_t command;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/* Create a slave device. */
|
||||||
|
SMBusDevice *smbus_device_init(i2c_bus *bus, int address, int size);
|
||||||
|
|
||||||
|
/* Master device commands. */
|
||||||
|
void smbus_quick_command(i2c_bus *bus, int addr, int read);
|
||||||
|
uint8_t smbus_receive_byte(i2c_bus *bus, int addr);
|
||||||
|
void smbus_send_byte(i2c_bus *bus, int addr, uint8_t data);
|
||||||
|
uint8_t smbus_read_byte(i2c_bus *bus, int addr, uint8_t command);
|
||||||
|
void smbus_write_byte(i2c_bus *bus, int addr, uint8_t command, uint8_t data);
|
||||||
|
uint16_t smbus_read_word(i2c_bus *bus, int addr, uint8_t command);
|
||||||
|
void smbus_write_word(i2c_bus *bus, int addr, uint8_t command, uint16_t data);
|
||||||
|
int smbus_read_block(i2c_bus *bus, int addr, uint8_t command, uint8_t *data);
|
||||||
|
void smbus_write_block(i2c_bus *bus, int addr, uint8_t command, uint8_t *data,
|
||||||
|
int len);
|
||||||
|
|
||||||
|
/* smbus_eeprom.c */
|
||||||
|
void smbus_eeprom_device_init(i2c_bus *bus, uint8_t addr, uint8_t *buf);
|
||||||
|
|
||||||
|
|
|
@ -58,37 +58,51 @@ static uint8_t eeprom_receive_byte(SMBusDevice *dev)
|
||||||
return val;
|
return val;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void eeprom_write_byte(SMBusDevice *dev, uint8_t cmd, uint8_t val)
|
static void eeprom_write_data(SMBusDevice *dev, uint8_t cmd, uint8_t *buf, int len)
|
||||||
{
|
{
|
||||||
SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev;
|
SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev;
|
||||||
|
int n;
|
||||||
#ifdef DEBUG
|
#ifdef DEBUG
|
||||||
printf("eeprom_write_byte: addr=0x%02x cmd=0x%02x val=0x%02x\n", dev->addr,
|
printf("eeprom_write_byte: addr=0x%02x cmd=0x%02x val=0x%02x\n", dev->addr,
|
||||||
cmd, val);
|
cmd, buf[0]);
|
||||||
#endif
|
#endif
|
||||||
eeprom->data[cmd] = val;
|
/* An page write operation is not a valid SMBus command.
|
||||||
|
It is a block write without a length byte. Fortunately we
|
||||||
|
get the full block anyway. */
|
||||||
|
/* TODO: Should this set the current location? */
|
||||||
|
if (cmd + len > 256)
|
||||||
|
n = 256 - cmd;
|
||||||
|
else
|
||||||
|
n = len;
|
||||||
|
memcpy(eeprom->data + cmd, buf, n);
|
||||||
|
len -= n;
|
||||||
|
if (len)
|
||||||
|
memcpy(eeprom->data, buf + n, len);
|
||||||
}
|
}
|
||||||
|
|
||||||
static uint8_t eeprom_read_byte(SMBusDevice *dev, uint8_t cmd)
|
static uint8_t eeprom_read_data(SMBusDevice *dev, uint8_t cmd, int n)
|
||||||
{
|
{
|
||||||
SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev;
|
SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev;
|
||||||
uint8_t val = eeprom->data[cmd];
|
/* If this is the first byte then set the current position. */
|
||||||
#ifdef DEBUG
|
if (n == 0)
|
||||||
printf("eeprom_read_byte: addr=0x%02x cmd=0x%02x val=0x%02x\n", dev->addr,
|
eeprom->offset = cmd;
|
||||||
cmd, val);
|
/* As with writes, we implement block reads without the
|
||||||
#endif
|
SMBus length byte. */
|
||||||
return val;
|
return eeprom_receive_byte(dev);
|
||||||
}
|
}
|
||||||
|
|
||||||
SMBusDevice *smbus_eeprom_device_init(uint8_t addr, uint8_t *buf)
|
void smbus_eeprom_device_init(i2c_bus *bus, uint8_t addr, uint8_t *buf)
|
||||||
{
|
{
|
||||||
SMBusEEPROMDevice *eeprom = qemu_mallocz(sizeof(SMBusEEPROMDevice));
|
SMBusEEPROMDevice *eeprom;
|
||||||
eeprom->dev.addr = addr;
|
|
||||||
|
eeprom = (SMBusEEPROMDevice *)smbus_device_init(bus, addr,
|
||||||
|
sizeof(SMBusEEPROMDevice));
|
||||||
|
|
||||||
eeprom->dev.quick_cmd = eeprom_quick_cmd;
|
eeprom->dev.quick_cmd = eeprom_quick_cmd;
|
||||||
eeprom->dev.send_byte = eeprom_send_byte;
|
eeprom->dev.send_byte = eeprom_send_byte;
|
||||||
eeprom->dev.receive_byte = eeprom_receive_byte;
|
eeprom->dev.receive_byte = eeprom_receive_byte;
|
||||||
eeprom->dev.write_byte = eeprom_write_byte;
|
eeprom->dev.write_data = eeprom_write_data;
|
||||||
eeprom->dev.read_byte = eeprom_read_byte;
|
eeprom->dev.read_data = eeprom_read_data;
|
||||||
eeprom->data = buf;
|
eeprom->data = buf;
|
||||||
eeprom->offset = 0;
|
eeprom->offset = 0;
|
||||||
return (SMBusDevice *) eeprom;
|
|
||||||
}
|
}
|
||||||
|
|
7
vl.h
7
vl.h
|
@ -1126,17 +1126,16 @@ int pit_get_out(PITState *pit, int channel, int64_t current_time);
|
||||||
void pcspk_init(PITState *);
|
void pcspk_init(PITState *);
|
||||||
int pcspk_audio_init(AudioState *, qemu_irq *pic);
|
int pcspk_audio_init(AudioState *, qemu_irq *pic);
|
||||||
|
|
||||||
|
#include "hw/i2c.h"
|
||||||
|
|
||||||
#include "hw/smbus.h"
|
#include "hw/smbus.h"
|
||||||
|
|
||||||
/* acpi.c */
|
/* acpi.c */
|
||||||
extern int acpi_enabled;
|
extern int acpi_enabled;
|
||||||
void piix4_pm_init(PCIBus *bus, int devfn);
|
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn);
|
||||||
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
|
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
|
||||||
void acpi_bios_init(void);
|
void acpi_bios_init(void);
|
||||||
|
|
||||||
/* smbus_eeprom.c */
|
|
||||||
SMBusDevice *smbus_eeprom_device_init(uint8_t addr, uint8_t *buf);
|
|
||||||
|
|
||||||
/* pc.c */
|
/* pc.c */
|
||||||
extern QEMUMachine pc_machine;
|
extern QEMUMachine pc_machine;
|
||||||
extern QEMUMachine isapc_machine;
|
extern QEMUMachine isapc_machine;
|
||||||
|
|
Loading…
Reference in a new issue