target/mips: simplify gen_compute_imm_branch logic
One of the Travis builds was complaining about: qemu/include/tcg/tcg.h:437:12: error: ‘cond’ may be used uninitialized in this function [-Werror=maybe-uninitialized] return (TCGCond)(c ^ 1); ../target/mips/translate.c:20031:13: note: ‘cond’ was declared here TCGCond cond; Rather than figure out exactly which one was causing the complaint I just defaulted to TCG_COND_ALWAYS and allowed that state to double up for the now defunct bcond_compute variable. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200909112742.25730-5-alex.bennee@linaro.org>
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@ -20028,8 +20028,7 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
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static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
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static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
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int rt, int32_t imm, int32_t offset)
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int rt, int32_t imm, int32_t offset)
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{
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{
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TCGCond cond;
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TCGCond cond = TCG_COND_ALWAYS;
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int bcond_compute = 0;
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TCGv t0 = tcg_temp_new();
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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@ -20046,7 +20045,6 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
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/* Treat as NOP */
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/* Treat as NOP */
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goto out;
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goto out;
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} else {
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} else {
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bcond_compute = 1;
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cond = TCG_COND_EQ;
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cond = TCG_COND_EQ;
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}
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}
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break;
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break;
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@ -20065,7 +20063,6 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
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tcg_gen_shri_tl(t0, t0, imm);
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tcg_gen_shri_tl(t0, t0, imm);
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tcg_gen_andi_tl(t0, t0, 1);
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tcg_gen_andi_tl(t0, t0, 1);
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tcg_gen_movi_tl(t1, 0);
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tcg_gen_movi_tl(t1, 0);
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bcond_compute = 1;
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if (opc == NM_BBEQZC) {
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if (opc == NM_BBEQZC) {
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cond = TCG_COND_EQ;
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cond = TCG_COND_EQ;
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} else {
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} else {
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@ -20080,7 +20077,6 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
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} else if (rt == 0 && imm != 0) {
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} else if (rt == 0 && imm != 0) {
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/* Unconditional branch */
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/* Unconditional branch */
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} else {
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} else {
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bcond_compute = 1;
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cond = TCG_COND_NE;
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cond = TCG_COND_NE;
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}
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}
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break;
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break;
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@ -20088,24 +20084,20 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
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if (rt == 0 && imm == 0) {
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if (rt == 0 && imm == 0) {
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/* Unconditional branch */
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/* Unconditional branch */
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} else {
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} else {
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bcond_compute = 1;
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cond = TCG_COND_GE;
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cond = TCG_COND_GE;
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}
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}
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break;
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break;
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case NM_BLTIC:
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case NM_BLTIC:
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bcond_compute = 1;
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cond = TCG_COND_LT;
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cond = TCG_COND_LT;
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break;
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break;
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case NM_BGEIUC:
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case NM_BGEIUC:
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if (rt == 0 && imm == 0) {
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if (rt == 0 && imm == 0) {
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/* Unconditional branch */
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/* Unconditional branch */
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} else {
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} else {
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bcond_compute = 1;
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cond = TCG_COND_GEU;
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cond = TCG_COND_GEU;
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}
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}
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break;
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break;
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case NM_BLTIUC:
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case NM_BLTIUC:
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bcond_compute = 1;
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cond = TCG_COND_LTU;
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cond = TCG_COND_LTU;
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break;
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break;
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default:
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default:
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@ -20118,7 +20110,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
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clear_branch_hflags(ctx);
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clear_branch_hflags(ctx);
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ctx->base.is_jmp = DISAS_NORETURN;
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ctx->base.is_jmp = DISAS_NORETURN;
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if (bcond_compute == 0) {
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if (cond == TCG_COND_ALWAYS) {
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/* Uncoditional compact branch */
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/* Uncoditional compact branch */
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gen_goto_tb(ctx, 0, ctx->btarget);
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gen_goto_tb(ctx, 0, ctx->btarget);
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} else {
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} else {
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