target-arm: Convert cp15 crn=15 registers
Convert the cp15 crn=15 (implementation specific) registers to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
parent
4fdd17dd35
commit
1047b9d7bb
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@ -71,7 +71,6 @@ static void arm_cpu_reset(CPUState *s)
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memset(env, 0, offsetof(CPUARMState, breakpoints));
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g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
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env->cp15.c15_config_base_address = cpu->reset_cbar;
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env->cp15.c0_cpuid = cpu->midr;
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env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
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env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
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@ -92,7 +91,6 @@ static void arm_cpu_reset(CPUState *s)
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env->cp15.c0_c2[3] = cpu->id_isar3;
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env->cp15.c0_c2[4] = cpu->id_isar4;
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env->cp15.c0_c2[5] = cpu->id_isar5;
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env->cp15.c15_i_min = 0xff0;
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env->cp15.c0_clid = cpu->clidr;
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memcpy(env->cp15.c0_ccsid, cpu->ccsidr, ARRAY_SIZE(cpu->ccsidr));
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@ -399,6 +397,35 @@ static void cortex_a8_initfn(Object *obj)
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cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
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}
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static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
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/* power_control should be set to maximum latency. Again,
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* default to 0 and set by private hook
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*/
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{ .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .resetvalue = 0,
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.fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
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{ .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
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.access = PL1_RW, .resetvalue = 0,
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.fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
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{ .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
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.access = PL1_RW, .resetvalue = 0,
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.fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
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{ .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
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/* TLB lockdown control */
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{ .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
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.access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
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{ .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
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.access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
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{ .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
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.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
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{ .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
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.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
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{ .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
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.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
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REGINFO_SENTINEL
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};
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static void cortex_a9_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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@ -434,6 +461,15 @@ static void cortex_a9_initfn(Object *obj)
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cpu->clidr = (1 << 27) | (1 << 24) | 3;
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cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
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cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
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{
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ARMCPRegInfo cbar = {
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.name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4,
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.opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
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.fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
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};
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define_one_arm_cp_reg(cpu, &cbar);
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define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
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}
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}
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static void cortex_a15_initfn(Object *obj)
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@ -386,6 +386,7 @@ enum arm_features {
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ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
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ARM_FEATURE_GENERIC_TIMER,
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ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
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ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
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};
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static inline int arm_feature(CPUARMState *env, int feature)
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@ -492,10 +492,91 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
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REGINFO_SENTINEL
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};
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static int omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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env->cp15.c15_ticonfig = value & 0xe7;
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/* The OS_TYPE bit in this register changes the reported CPUID! */
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env->cp15.c0_cpuid = (value & (1 << 5)) ?
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ARM_CPUID_TI915T : ARM_CPUID_TI925T;
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return 0;
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}
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static int omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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env->cp15.c15_threadid = value & 0xffff;
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return 0;
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}
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static int omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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/* Wait-for-interrupt (deprecated) */
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cpu_interrupt(env, CPU_INTERRUPT_HALT);
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return 0;
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}
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static const ARMCPRegInfo omap_cp_reginfo[] = {
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{ .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
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.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
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.fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
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{ .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_NOP },
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{ .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW,
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.fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
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.writefn = omap_ticonfig_write },
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{ .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW,
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.fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
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{ .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .resetvalue = 0xff0,
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.fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
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{ .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW,
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.fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
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.writefn = omap_threadid_write },
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{ .name = "TI925T_STATUS", .cp = 15, .crn = 15,
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.crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
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.readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
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/* TODO: Peripheral port remap register:
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* On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
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* base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
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* when MMU is off.
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*/
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REGINFO_SENTINEL
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};
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static int xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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value &= 0x3fff;
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if (env->cp15.c15_cpar != value) {
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/* Changes cp0 to cp13 behavior, so needs a TB flush. */
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tb_flush(env);
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env->cp15.c15_cpar = value;
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}
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return 0;
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}
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static const ARMCPRegInfo xscale_cp_reginfo[] = {
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{ .name = "XSCALE_CPAR",
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.cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
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.fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
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.writefn = xscale_cpar_write, },
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REGINFO_SENTINEL
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};
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static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
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/* RAZ/WI the whole crn=15 space, when we don't have a more specific
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* implementation of this implementation-defined space.
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* Ideally this should eventually disappear in favour of actually
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* implementing the correct behaviour for all cores.
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*/
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{ .name = "C15_IMPDEF", .cp = 15, .crn = 15,
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.crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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REGINFO_SENTINEL
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};
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@ -552,6 +633,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
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define_arm_cp_regs(cpu, omap_cp_reginfo);
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}
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if (arm_feature(env, ARM_FEATURE_XSCALE)) {
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define_arm_cp_regs(cpu, xscale_cp_reginfo);
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}
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if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
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define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
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}
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}
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ARMCPU *cpu_arm_init(const char *cpu_model)
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@ -1802,58 +1889,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
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break;
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case 12: /* Reserved. */
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goto bad_reg;
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case 15: /* Implementation specific. */
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if (arm_feature(env, ARM_FEATURE_XSCALE)) {
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if (op2 == 0 && crm == 1) {
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if (env->cp15.c15_cpar != (val & 0x3fff)) {
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/* Changes cp0 to cp13 behavior, so needs a TB flush. */
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tb_flush(env);
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env->cp15.c15_cpar = val & 0x3fff;
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}
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break;
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}
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goto bad_reg;
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}
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if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
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switch (crm) {
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case 0:
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break;
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case 1: /* Set TI925T configuration. */
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env->cp15.c15_ticonfig = val & 0xe7;
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env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */
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ARM_CPUID_TI915T : ARM_CPUID_TI925T;
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break;
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case 2: /* Set I_max. */
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env->cp15.c15_i_max = val;
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break;
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case 3: /* Set I_min. */
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env->cp15.c15_i_min = val;
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break;
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case 4: /* Set thread-ID. */
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env->cp15.c15_threadid = val & 0xffff;
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break;
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case 8: /* Wait-for-interrupt (deprecated). */
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cpu_interrupt(env, CPU_INTERRUPT_HALT);
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break;
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default:
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goto bad_reg;
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}
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}
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if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
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switch (crm) {
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case 0:
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if ((op1 == 0) && (op2 == 0)) {
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env->cp15.c15_power_control = val;
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} else if ((op1 == 0) && (op2 == 1)) {
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env->cp15.c15_diagnostic = val;
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} else if ((op1 == 0) && (op2 == 2)) {
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env->cp15.c15_power_diagnostic = val;
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}
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default:
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break;
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}
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}
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break;
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}
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return;
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bad_reg:
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@ -2080,69 +2115,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
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case 11: /* TCM DMA control. */
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case 12: /* Reserved. */
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goto bad_reg;
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case 15: /* Implementation specific. */
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if (arm_feature(env, ARM_FEATURE_XSCALE)) {
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if (op2 == 0 && crm == 1)
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return env->cp15.c15_cpar;
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goto bad_reg;
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}
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if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
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switch (crm) {
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case 0:
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return 0;
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case 1: /* Read TI925T configuration. */
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return env->cp15.c15_ticonfig;
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case 2: /* Read I_max. */
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return env->cp15.c15_i_max;
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case 3: /* Read I_min. */
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return env->cp15.c15_i_min;
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case 4: /* Read thread-ID. */
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return env->cp15.c15_threadid;
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case 8: /* TI925T_status */
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return 0;
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}
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/* TODO: Peripheral port remap register:
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* On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
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* controller base address at $rn & ~0xfff and map size of
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* 0x200 << ($rn & 0xfff), when MMU is off. */
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goto bad_reg;
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}
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if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
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switch (crm) {
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case 0:
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if ((op1 == 4) && (op2 == 0)) {
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/* The config_base_address should hold the value of
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* the peripheral base. ARM should get this from a CPU
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* object property, but that support isn't available in
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* December 2011. Default to 0 for now and board models
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* that care can set it by a private hook */
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return env->cp15.c15_config_base_address;
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} else if ((op1 == 0) && (op2 == 0)) {
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/* power_control should be set to maximum latency. Again,
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default to 0 and set by private hook */
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return env->cp15.c15_power_control;
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} else if ((op1 == 0) && (op2 == 1)) {
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return env->cp15.c15_diagnostic;
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} else if ((op1 == 0) && (op2 == 2)) {
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return env->cp15.c15_power_diagnostic;
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}
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break;
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case 1: /* NEON Busy */
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return 0;
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case 5: /* tlb lockdown */
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case 6:
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case 7:
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if ((op1 == 5) && (op2 == 2)) {
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return 0;
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}
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break;
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default:
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break;
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}
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goto bad_reg;
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}
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return 0;
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}
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bad_reg:
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/* ??? For debugging only. Should raise illegal instruction exception. */
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