dwc-hsotg (dwc2) USB host controller state definitions
Add the dwc-hsotg (dwc2) USB host controller state definitions. Mostly based on hw/usb/hcd-ehci.h. Signed-off-by: Paul Zimmerman <pauldzim@gmail.com> Message-id: 20200520235349.21215-4-pauldzim@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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hw/usb/hcd-dwc2.h
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hw/usb/hcd-dwc2.h
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/*
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* dwc-hsotg (dwc2) USB host controller state definitions
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*
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* Based on hw/usb/hcd-ehci.h
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*
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* Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef HW_USB_DWC2_H
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#define HW_USB_DWC2_H
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#include "qemu/timer.h"
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#include "hw/irq.h"
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#include "hw/sysbus.h"
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#include "hw/usb.h"
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#include "sysemu/dma.h"
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#define DWC2_MMIO_SIZE 0x11000
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#define DWC2_NB_CHAN 8 /* Number of host channels */
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#define DWC2_MAX_XFER_SIZE 65536 /* Max transfer size expected in HCTSIZ */
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typedef struct DWC2Packet DWC2Packet;
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typedef struct DWC2State DWC2State;
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typedef struct DWC2Class DWC2Class;
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enum async_state {
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DWC2_ASYNC_NONE = 0,
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DWC2_ASYNC_INITIALIZED,
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DWC2_ASYNC_INFLIGHT,
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DWC2_ASYNC_FINISHED,
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};
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struct DWC2Packet {
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USBPacket packet;
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uint32_t devadr;
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uint32_t epnum;
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uint32_t epdir;
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uint32_t mps;
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uint32_t pid;
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uint32_t index;
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uint32_t pcnt;
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uint32_t len;
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int32_t async;
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bool small;
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bool needs_service;
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};
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struct DWC2State {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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USBBus bus;
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qemu_irq irq;
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MemoryRegion *dma_mr;
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AddressSpace dma_as;
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MemoryRegion container;
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MemoryRegion hsotg;
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MemoryRegion fifos;
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union {
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#define DWC2_GLBREG_SIZE 0x70
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uint32_t glbreg[DWC2_GLBREG_SIZE / sizeof(uint32_t)];
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struct {
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uint32_t gotgctl; /* 00 */
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uint32_t gotgint; /* 04 */
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uint32_t gahbcfg; /* 08 */
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uint32_t gusbcfg; /* 0c */
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uint32_t grstctl; /* 10 */
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uint32_t gintsts; /* 14 */
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uint32_t gintmsk; /* 18 */
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uint32_t grxstsr; /* 1c */
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uint32_t grxstsp; /* 20 */
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uint32_t grxfsiz; /* 24 */
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uint32_t gnptxfsiz; /* 28 */
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uint32_t gnptxsts; /* 2c */
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uint32_t gi2cctl; /* 30 */
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uint32_t gpvndctl; /* 34 */
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uint32_t ggpio; /* 38 */
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uint32_t guid; /* 3c */
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uint32_t gsnpsid; /* 40 */
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uint32_t ghwcfg1; /* 44 */
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uint32_t ghwcfg2; /* 48 */
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uint32_t ghwcfg3; /* 4c */
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uint32_t ghwcfg4; /* 50 */
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uint32_t glpmcfg; /* 54 */
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uint32_t gpwrdn; /* 58 */
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uint32_t gdfifocfg; /* 5c */
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uint32_t gadpctl; /* 60 */
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uint32_t grefclk; /* 64 */
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uint32_t gintmsk2; /* 68 */
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uint32_t gintsts2; /* 6c */
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};
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};
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union {
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#define DWC2_FSZREG_SIZE 0x04
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uint32_t fszreg[DWC2_FSZREG_SIZE / sizeof(uint32_t)];
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struct {
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uint32_t hptxfsiz; /* 100 */
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};
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};
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union {
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#define DWC2_HREG0_SIZE 0x44
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uint32_t hreg0[DWC2_HREG0_SIZE / sizeof(uint32_t)];
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struct {
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uint32_t hcfg; /* 400 */
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uint32_t hfir; /* 404 */
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uint32_t hfnum; /* 408 */
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uint32_t rsvd0; /* 40c */
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uint32_t hptxsts; /* 410 */
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uint32_t haint; /* 414 */
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uint32_t haintmsk; /* 418 */
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uint32_t hflbaddr; /* 41c */
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uint32_t rsvd1[8]; /* 420-43c */
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uint32_t hprt0; /* 440 */
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};
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};
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#define DWC2_HREG1_SIZE (0x20 * DWC2_NB_CHAN)
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uint32_t hreg1[DWC2_HREG1_SIZE / sizeof(uint32_t)];
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#define hcchar(_ch) hreg1[((_ch) << 3) + 0] /* 500, 520, ... */
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#define hcsplt(_ch) hreg1[((_ch) << 3) + 1] /* 504, 524, ... */
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#define hcint(_ch) hreg1[((_ch) << 3) + 2] /* 508, 528, ... */
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#define hcintmsk(_ch) hreg1[((_ch) << 3) + 3] /* 50c, 52c, ... */
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#define hctsiz(_ch) hreg1[((_ch) << 3) + 4] /* 510, 530, ... */
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#define hcdma(_ch) hreg1[((_ch) << 3) + 5] /* 514, 534, ... */
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#define hcdmab(_ch) hreg1[((_ch) << 3) + 7] /* 51c, 53c, ... */
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union {
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#define DWC2_PCGREG_SIZE 0x08
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uint32_t pcgreg[DWC2_PCGREG_SIZE / sizeof(uint32_t)];
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struct {
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uint32_t pcgctl; /* e00 */
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uint32_t pcgcctl1; /* e04 */
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};
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};
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/* TODO - implement FIFO registers for slave mode */
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#define DWC2_HFIFO_SIZE (0x1000 * DWC2_NB_CHAN)
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/*
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* Internal state
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*/
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QEMUTimer *eof_timer;
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QEMUTimer *frame_timer;
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QEMUBH *async_bh;
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int64_t sof_time;
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int64_t usb_frame_time;
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int64_t usb_bit_time;
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uint32_t usb_version;
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uint16_t frame_number;
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uint16_t fi;
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uint16_t next_chan;
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bool working;
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USBPort uport;
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DWC2Packet packet[DWC2_NB_CHAN]; /* one packet per chan */
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uint8_t usb_buf[DWC2_NB_CHAN][DWC2_MAX_XFER_SIZE]; /* one buffer per chan */
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};
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struct DWC2Class {
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/*< private >*/
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SysBusDeviceClass parent_class;
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ResettablePhases parent_phases;
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/*< public >*/
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};
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#define TYPE_DWC2_USB "dwc2-usb"
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#define DWC2_USB(obj) \
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OBJECT_CHECK(DWC2State, (obj), TYPE_DWC2_USB)
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#define DWC2_CLASS(klass) \
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OBJECT_CLASS_CHECK(DWC2Class, (klass), TYPE_DWC2_USB)
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#define DWC2_GET_CLASS(obj) \
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OBJECT_GET_CLASS(DWC2Class, (obj), TYPE_DWC2_USB)
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#endif
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