From 10ca2943aab6646839769d78f80b0d5499efcbe9 Mon Sep 17 00:00:00 2001 From: David Gibson Date: Wed, 27 Jun 2012 14:50:41 +1000 Subject: [PATCH] ide/ahci: Use universal DMA helper functions The AHCI device can provide both PCI and SysBus AHCI device emulations. For this reason, it wasn't previously converted to use the pci_dma_*() helper functions. Now that we have universal DMA helper functions, this converts AHCI to use them. The DMAContext is obtained from pci_dma_context() in the PCI case and set to NULL in the SysBus case (i.e. we assume for now that a SysBus AHCI has no IOMMU translation). Cc: Kevin Wolf Cc: Michael S. Tsirkin Signed-off-by: David Gibson Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Anthony Liguori --- hw/ide/ahci.c | 34 ++++++++++++++++++++-------------- hw/ide/ahci.h | 3 ++- hw/ide/ich.c | 2 +- 3 files changed, 23 insertions(+), 16 deletions(-) diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index 6c4226da82..efea93f0b4 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -588,7 +588,7 @@ static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis) AHCIPortRegs *pr = &ad->port_regs; uint8_t *d2h_fis; int i; - target_phys_addr_t cmd_len = 0x80; + dma_addr_t cmd_len = 0x80; int cmd_mapped = 0; if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { @@ -598,7 +598,8 @@ static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis) if (!cmd_fis) { /* map cmd_fis */ uint64_t tbl_addr = le64_to_cpu(ad->cur_cmd->tbl_addr); - cmd_fis = cpu_physical_memory_map(tbl_addr, &cmd_len, 0); + cmd_fis = dma_memory_map(ad->hba->dma, tbl_addr, &cmd_len, + DMA_DIRECTION_TO_DEVICE); cmd_mapped = 1; } @@ -630,7 +631,8 @@ static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis) ahci_trigger_irq(ad->hba, ad, PORT_IRQ_D2H_REG_FIS); if (cmd_mapped) { - cpu_physical_memory_unmap(cmd_fis, cmd_len, 0, cmd_len); + dma_memory_unmap(ad->hba->dma, cmd_fis, cmd_len, + DMA_DIRECTION_TO_DEVICE, cmd_len); } } @@ -640,8 +642,8 @@ static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist) uint32_t opts = le32_to_cpu(cmd->opts); uint64_t prdt_addr = le64_to_cpu(cmd->tbl_addr) + 0x80; int sglist_alloc_hint = opts >> AHCI_CMD_HDR_PRDT_LEN; - target_phys_addr_t prdt_len = (sglist_alloc_hint * sizeof(AHCI_SG)); - target_phys_addr_t real_prdt_len = prdt_len; + dma_addr_t prdt_len = (sglist_alloc_hint * sizeof(AHCI_SG)); + dma_addr_t real_prdt_len = prdt_len; uint8_t *prdt; int i; int r = 0; @@ -652,7 +654,8 @@ static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist) } /* map PRDT */ - if (!(prdt = cpu_physical_memory_map(prdt_addr, &prdt_len, 0))){ + if (!(prdt = dma_memory_map(ad->hba->dma, prdt_addr, &prdt_len, + DMA_DIRECTION_TO_DEVICE))){ DPRINTF(ad->port_no, "map failed\n"); return -1; } @@ -667,8 +670,7 @@ static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist) if (sglist_alloc_hint > 0) { AHCI_SG *tbl = (AHCI_SG *)prdt; - /* FIXME: pass the correct DMAContext */ - qemu_sglist_init(sglist, sglist_alloc_hint, NULL); + qemu_sglist_init(sglist, sglist_alloc_hint, ad->hba->dma); for (i = 0; i < sglist_alloc_hint; i++) { /* flags_size is zero-based */ qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr), @@ -677,7 +679,8 @@ static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist) } out: - cpu_physical_memory_unmap(prdt, prdt_len, 0, prdt_len); + dma_memory_unmap(ad->hba->dma, prdt, prdt_len, + DMA_DIRECTION_TO_DEVICE, prdt_len); return r; } @@ -787,7 +790,7 @@ static int handle_cmd(AHCIState *s, int port, int slot) uint64_t tbl_addr; AHCICmdHdr *cmd; uint8_t *cmd_fis; - target_phys_addr_t cmd_len; + dma_addr_t cmd_len; if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { /* Engine currently busy, try again later */ @@ -809,7 +812,8 @@ static int handle_cmd(AHCIState *s, int port, int slot) tbl_addr = le64_to_cpu(cmd->tbl_addr); cmd_len = 0x80; - cmd_fis = cpu_physical_memory_map(tbl_addr, &cmd_len, 1); + cmd_fis = dma_memory_map(s->dma, tbl_addr, &cmd_len, + DMA_DIRECTION_FROM_DEVICE); if (!cmd_fis) { DPRINTF(port, "error: guest passed us an invalid cmd fis\n"); @@ -935,7 +939,8 @@ static int handle_cmd(AHCIState *s, int port, int slot) } out: - cpu_physical_memory_unmap(cmd_fis, cmd_len, 1, cmd_len); + dma_memory_unmap(s->dma, cmd_fis, cmd_len, DMA_DIRECTION_FROM_DEVICE, + cmd_len); if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { /* async command, complete later */ @@ -1115,11 +1120,12 @@ static const IDEDMAOps ahci_dma_ops = { .reset = ahci_dma_reset, }; -void ahci_init(AHCIState *s, DeviceState *qdev, int ports) +void ahci_init(AHCIState *s, DeviceState *qdev, DMAContext *dma, int ports) { qemu_irq *irqs; int i; + s->dma = dma; s->ports = ports; s->dev = g_malloc0(sizeof(AHCIDevice) * ports); ahci_reg_init(s); @@ -1188,7 +1194,7 @@ static void sysbus_ahci_reset(DeviceState *dev) static int sysbus_ahci_init(SysBusDevice *dev) { SysbusAHCIState *s = FROM_SYSBUS(SysbusAHCIState, dev); - ahci_init(&s->ahci, &dev->qdev, s->num_ports); + ahci_init(&s->ahci, &dev->qdev, NULL, s->num_ports); sysbus_init_mmio(dev, &s->ahci.mem); sysbus_init_irq(dev, &s->ahci.irq); diff --git a/hw/ide/ahci.h b/hw/ide/ahci.h index ec1b6a5f66..1200a56ada 100644 --- a/hw/ide/ahci.h +++ b/hw/ide/ahci.h @@ -299,6 +299,7 @@ typedef struct AHCIState { uint32_t idp_index; /* Current IDP index */ int ports; qemu_irq irq; + DMAContext *dma; } AHCIState; typedef struct AHCIPCIState { @@ -329,7 +330,7 @@ typedef struct NCQFrame { uint8_t reserved10; } QEMU_PACKED NCQFrame; -void ahci_init(AHCIState *s, DeviceState *qdev, int ports); +void ahci_init(AHCIState *s, DeviceState *qdev, DMAContext *dma, int ports); void ahci_uninit(AHCIState *s); void ahci_reset(AHCIState *s); diff --git a/hw/ide/ich.c b/hw/ide/ich.c index e3eaaea882..319bc2bb10 100644 --- a/hw/ide/ich.c +++ b/hw/ide/ich.c @@ -98,7 +98,7 @@ static int pci_ich9_ahci_init(PCIDevice *dev) uint8_t *sata_cap; d = DO_UPCAST(struct AHCIPCIState, card, dev); - ahci_init(&d->ahci, &dev->qdev, 6); + ahci_init(&d->ahci, &dev->qdev, pci_dma_context(dev), 6); pci_config_set_prog_interface(d->card.config, AHCI_PROGMODE_MAJOR_REV_1);