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target-ppc: Altivec 2.07: Vector Logical Instructions

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This patch adds the Vector Logical Instructions that are introduced
in Power ISA Version 2.07: veqv, vnand and vorc.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Tom Musta 2014-02-12 15:22:58 -06:00 committed by Alexander Graf
parent a737d3ebc8
commit 111c5f54a1
1 changed files with 11 additions and 0 deletions
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11
target-ppc/translate.c
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@ -6852,6 +6852,9 @@ GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
#define GEN_VXFORM(name, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
@ -10301,11 +10304,19 @@ GEN_VR_STVE(wx, 0x07, 0x06),
#undef GEN_VX_LOGICAL
#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
#undef GEN_VX_LOGICAL_207
#define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
#undef GEN_VXFORM
#define GEN_VXFORM(name, opc2, opc3) \